/**
* Enable Message-based C1e
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
InitializeMsgBasedC1eFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
AMD_CPU_EARLY_PARAMS CpuEarlyParams;
IDS_HDT_CONSOLE (CPU_TRACE, " MT C1e is enabled\n");
if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) {
CpuEarlyParams.PlatformConfig = *PlatformConfig;
TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &EntryPoint;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
}
return AGESA_SUCCESS;
}
/**
* Initialize Machine Check Architecture registers
*
* This function initializes the MCA MSRs. On cold reset, these registers
* have an invalid data that must be cleared on all cores.
*
* @param[in] StdHeader Config handle for library and services
*
*---------------------------------------------------------------------------------------
*/
VOID
McaInitialization (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 TempVar16_a;
UINT32 MsrAddress;
UINT64 MsrData;
CPUID_DATA CpuIdDataStruct;
if (!(IsWarmReset (StdHeader))) {
// Run CPUID to verify that the processor supports MCE and MCA
// i.e. edx[7], and edx[14]
// CPUID_MODEL = 1
LibAmdCpuidRead (1, &CpuIdDataStruct, StdHeader);
if ((CpuIdDataStruct.EDX_Reg & 0x4080) != 0) {
// Check to see if the MCG_CTL_P bit is set
// MCG = Global Machine Check Exception Reporting Control Register
LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
if ((MsrData & MCG_CTL_P) != 0) {
TempVar16_a = (UINT16) ((MsrData & 0x000000FF) << 2);
TempVar16_a += MSR_MC0_CTL;
// Initialize the data
MsrData = 0;
for (MsrAddress = MSR_MC0_CTL; MsrAddress < TempVar16_a; MsrAddress++) {
LibAmdMsrWrite (MsrAddress, &MsrData, StdHeader);
}
}
}
}
}
/**
* Get current condition, such as warm/cold reset, to determine if related function
* need to be performed at early stage
*
* @param[in, out] PerformEarlyFlag Perform early flag.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
GetPerformEarlyFlag (
IN OUT UINT32 *PerformEarlyFlag,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*PerformEarlyFlag = 0;
if (IsWarmReset (StdHeader)) {
*PerformEarlyFlag |= PERFORM_EARLY_WARM_RESET;
} else {
*PerformEarlyFlag |= PERFORM_EARLY_COLD_BOOT;
}
return;
}
/**
* Performs the next step in the executing core 0's family specific power
* management table.
*
* This function determines if the input step is valid, and invokes the power
* management step if appropriate. This must be run by processor core 0s only.
*
* @param[in] Step Zero based step number
* @param[in] StdHeader Config handle for library and services
* @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization
*
*/
VOID
STATIC
PerformThisPmStep (
IN VOID *Step,
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
)
{
UINT8 MyNumberOfSteps;
UINT32 ExeResetFlags;
SYS_PM_TBL_STEP *FamilyTablePtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
BOOLEAN ThisIsWarmReset;
BOOLEAN NoResetLimit;
BOOLEAN NotConflictResetLimit;
BOOLEAN WarmResetOnly;
BOOLEAN ColdResetOnly;
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &FamilyTablePtr, &MyNumberOfSteps, StdHeader);
if (*(UINT8 *)Step < MyNumberOfSteps) {
if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) {
ExeResetFlags = FamilyTablePtr[*(UINT8 *)Step].ExeFlags & (PM_EXEFLAGS_COLD_ONLY | PM_EXEFLAGS_WARM_ONLY);
ThisIsWarmReset = IsWarmReset (StdHeader);
NoResetLimit = (ExeResetFlags == 0) ? TRUE : FALSE;
NotConflictResetLimit = (BOOLEAN) (ExeResetFlags != (PM_EXEFLAGS_COLD_ONLY | PM_EXEFLAGS_WARM_ONLY));
WarmResetOnly = (BOOLEAN) ((ExeResetFlags & PM_EXEFLAGS_WARM_ONLY) == PM_EXEFLAGS_WARM_ONLY);
ColdResetOnly = (BOOLEAN) ((ExeResetFlags & PM_EXEFLAGS_COLD_ONLY) == PM_EXEFLAGS_COLD_ONLY);
IDS_HDT_CONSOLE (CPU_TRACE, " \tIsWarmReset = %d.\n", ThisIsWarmReset);
IDS_HDT_CONSOLE (CPU_TRACE, " \tNoResetLimit = %d\n", NoResetLimit);
IDS_HDT_CONSOLE (CPU_TRACE, " \tNotConflictResetLimit = %d\n", NotConflictResetLimit);
IDS_HDT_CONSOLE (CPU_TRACE, " \tWarmResetOnly = %d\n", WarmResetOnly);
IDS_HDT_CONSOLE (CPU_TRACE, " \tColdResetOnly = %d\n", ColdResetOnly);
ASSERT (NotConflictResetLimit);
if (NoResetLimit ||
(NotConflictResetLimit &&
((WarmResetOnly && ThisIsWarmReset) || (ColdResetOnly && !ThisIsWarmReset)))) {
FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader);
} else {
IDS_HDT_CONSOLE (CPU_TRACE, " \t\tThis PM init step was skipped!\n");
}
}
}
}
/**
* This function will set the CPU register warm reset bits at AmdInitEarly if it is
* currently in cold boot. To request for a warm reset, set the RequestBit to TRUE
* and the StateBits to (current poststage - 1)
*
* @param[in] Data The table data value (unused in this routine)
* @param[in] StdHeader Config handle for library and services
*
*---------------------------------------------------------------------------------------
**/
VOID
SetWarmResetAtEarly (
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
WARM_RESET_REQUEST Request;
if (!IsWarmReset (StdHeader)) {
GetWarmResetFlag (StdHeader, &Request);
Request.RequestBit = TRUE;
Request.StateBits = (Request.PostStage - 1);
SetWarmResetFlag (StdHeader, &Request);
}
}
/**
* Enable high performance computing (HPC mode)
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
InitializePstateHpcModeFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
if (!IsWarmReset (StdHeader)) {
IDS_HDT_CONSOLE (CPU_TRACE, " P-state HPC mode is enabled\n");
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
TaskPtr.FuncAddress.PfApTaskI = EnablePstateHpcModeOnAps;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = PlatformConfig;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
}
}
EnablePstateHpcModeOnAps (PlatformConfig, StdHeader);
}
return AGESA_SUCCESS;
}
/**
* Enable Software C1e
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return The most severe status of any family specific service.
*
*/
AGESA_STATUS
STATIC
InitializeSwC1eFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
SW_C1E_FAMILY_SERVICES *FamilyServices;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (CPU_TRACE, " SW C1e is enabled\n");
if (IsWarmReset (StdHeader)) {
GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &FamilyServices, StdHeader);
AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
}
return AgesaStatus;
}
/**
* Enable Hardware C1e
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return The most severe status of any family specific service.
*
*/
AGESA_STATUS
STATIC
InitializeHwC1eFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS CalledStatus;
AGESA_STATUS AgesaStatus;
HW_C1E_FAMILY_SERVICES *FamilyServices;
AgesaStatus = AGESA_SUCCESS;
if (IsWarmReset (StdHeader)) {
GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
if (CalledStatus > AgesaStatus) {
AgesaStatus = CalledStatus;
}
}
return AgesaStatus;
}
/**
* Performs the next step in the executing core 0's family specific power
* management table.
*
* This function determines if the input step is valid, and invokes the power
* management step if appropriate. This must be run by processor core 0s only.
*
* @param[in] Step Zero based step number
* @param[in] StdHeader Config handle for library and services
* @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization
*
*/
VOID
STATIC
PerformThisPmStep (
IN VOID *Step,
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
)
{
UINT8 MyNumberOfSteps;
SYS_PM_TBL_STEP *FamilyTablePtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &FamilyTablePtr, &MyNumberOfSteps, StdHeader);
if (*(UINT8 *)Step < MyNumberOfSteps) {
if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) {
if (!(BOOLEAN) (FamilyTablePtr[*(UINT8 *)Step].ExeFlags & PM_EXEFLAGS_WARM_ONLY) ||
IsWarmReset (StdHeader)) {
FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader);
}
}
}
}
/**
* Save and Restore or Initialize the content of the mailbox registers.
*
* The registers used for AP mailbox should have the content related to their function
* preserved.
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
PreserveMailboxes (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices;
UINT32 Socket;
UINT32 Module;
PCI_ADDR BaseAddress;
PCI_ADDR MailboxRegister;
PCI_ADDR *NextRegister;
AGESA_STATUS IgnoredStatus;
AGESA_STATUS HeapStatus;
UINT32 Value;
ALLOCATE_HEAP_PARAMS AllocateParams;
LOCATE_HEAP_PTR LocateParams;
UINT32 RegisterEntryIndex;
BaseAddress.AddressValue = ILLEGAL_SBDFO;
if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) {
// The save step. Save either the register content or zero (for cold boot, if family specifies that).
AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES)));
AllocateParams.Persist = HEAP_SYSTEM_MEM;
HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader);
ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL));
LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader);
RegisterEntryIndex = 0;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
NextRegister = FamilySpecificServices->RegisterList;
while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
ASSERT (RegisterEntryIndex <
(MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) {
Value = 0;
} else {
MailboxRegister = BaseAddress;
MailboxRegister.Address.Function = NextRegister->Address.Function;
MailboxRegister.Address.Register = NextRegister->Address.Register;
LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);
}
(* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value;
RegisterEntryIndex++;
NextRegister++;
}
}
}
}
} else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) {
// The restore step. Just write out the saved content in the buffer.
LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader);
ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL));
RegisterEntryIndex = 0;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
NextRegister = FamilySpecificServices->RegisterList;
while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
ASSERT (RegisterEntryIndex <
(MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
MailboxRegister = BaseAddress;
MailboxRegister.Address.Function = NextRegister->Address.Function;
MailboxRegister.Address.Register = NextRegister->Address.Register;
Value = (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex];
LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader);
RegisterEntryIndex++;
NextRegister++;
}
}
}
}
HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader);
}
return AGESA_SUCCESS;
}
/**
* Family 10h core 0 entry point for performing power plane initialization.
*
* The steps are as follows:
* 1. If single plane, program lower VID code of CpuVid & NbVid for all
* enabled P-States.
* 2. Configure F3xA0[SlamMode] & F3xD8[VsRampTime & VsSlamTime] based on
* platform requirements.
* 3. Configure F3xD4[PowerStepUp & PowerStepDown]
* 4. Optionally configure F3xA0[PsiVidEn & PsiVid]
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10CpuAmdPmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN PviModeFlag;
PCI_ADDR PciAddress;
UINT16 PowerStepTime;
UINT32 PowerStepEncoded;
UINT32 PciRegister;
UINT32 VsSlamTime;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 NumOfCores;
UINT32 LowCore;
UINT32 AndMask;
UINT32 OrMask;
UINT64 MsrRegister;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PLATFORM_FEATS Features;
CPU_LOGICAL_ID LogicalId;
// Initialize the union
Features.PlatformValue = 0;
GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader);
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
ASSERT (Core == 0);
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
// Set SlamVidMode
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = PW_CTL_MISC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
AndMask = 0xFFFFFFFF;
OrMask = 0x00000000;
if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
PviModeFlag = TRUE;
((POWER_CTRL_MISC_REGISTER *) &AndMask)->SlamVidMode = 0;
// Have all single plane cores adjust their NB and CPU VID fields
TaskPtr.FuncAddress.PfApTask = F10PmPwrPlaneInitPviCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
} else {
PviModeFlag = FALSE;
((POWER_CTRL_MISC_REGISTER *) &OrMask)->SlamVidMode = 1;
}
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
// Configure PowerStepUp/PowerStepDown
PciAddress.Address.Register = CPTC0_REG;
if ((Features.PlatformFeatures.PlatformSingleLink == 1) ||
(Features.PlatformFeatures.PlatformUma == 1) ||
(Features.PlatformFeatures.PlatformUmaIfcm == 1) ||
(Features.PlatformFeatures.PlatformIfcm == 1) ||
(Features.PlatformFeatures.PlatformIommu == 1)) {
PowerStepEncoded = 0x8;
} else {
GetGivenModuleCoreRange ((UINT32) Socket,
(UINT32) Module,
&LowCore,
&NumOfCores,
StdHeader);
NumOfCores = ((NumOfCores - LowCore) + 1);
PowerStepTime = (UINT16) (400 / NumOfCores);
for (PowerStepEncoded = 0xF; PowerStepEncoded > 0; PowerStepEncoded--) {
if (PowerStepTime <= PowerStepEncodings[PowerStepEncoded]) {
break;
}
}
}
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = PowerStepEncoded;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = PowerStepEncoded;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
if ((LogicalId.Revision & AMD_F10_C3) != 0) {
// Set up Pop up P-state register
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
AndMask = 0xFFFFFFFF;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupPstate = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuVid = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuFid = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuDid = 0;
OrMask = 0x00000000;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader);
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid;
PciAddress.Address.Register = POPUP_PSTATE_REG;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Set AltVidStart
PciAddress.Address.Register = CPTC1_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Set up Altvid slam time
PciAddress.Address.Register = CPTC2_REG;
VsSlamTime = F10CalculateAltvidVSSlamTimeOnCore (PviModeFlag, &PciAddress, CpuEarlyParams, StdHeader);
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->AltvidVSSlamTime = 0;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->SlamTimeMode = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->AltvidVSSlamTime = VsSlamTime;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->SlamTimeMode = 2;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
}
if (IsWarmReset (StdHeader) && !PviModeFlag) {
// Configure PsiVid
F10PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
}
}
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
*
* The steps are as follows:
* 1. Determine if the algorithm is necessary by checking if all NB FIDs
* match in the coherent fabric. If so, check to see if NbCofVidUpdate
* is zero for all CPUs. If that is also true, no further steps are
* necessary. If not + cold reset, proceed to step 2. If not + warm
* reset, proceed to step 8.
* 2. Determine NewNbVid & NewNbFid.
* 3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
* 4. Copy NewNbVid to P0 NbVid on all local cores.
* 5. Transition to P1 on all local cores.
* 6. Transition to P0 on local core 0 only.
* 7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
* 8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
* on all local cores.
* 9. Transition to Startup Pstate on all local cores.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmNbCofVidInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN PerformNbCofVidCfg;
BOOLEAN SystemNbCofsMatch;
UINT8 NewNbFid;
UINT8 NewNbVid;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 SystemNbCof;
UINT32 AndMask;
UINT32 OrMask;
UINT32 Ignored;
UINT32 NewNbVoltage;
WARM_RESET_REQUEST Request;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
NB_COF_VID_INIT_WARM FunctionData;
PerformNbCofVidCfg = TRUE;
OptionMultiSocketConfiguration.GetSystemNbCof (&SystemNbCof, &SystemNbCofsMatch, StdHeader);
if (SystemNbCofsMatch) {
if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
PerformNbCofVidCfg = FALSE;
}
}
if (PerformNbCofVidCfg) {
// get the local node ID
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
ASSERT (Core == 0);
// get NewNbVid
FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, &Ignored, &NewNbVoltage, StdHeader);
ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
ASSERT (NewNbVid < 0x80);
if (!(IsWarmReset (StdHeader))) {
// determine NewNbFid
NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &NewNbVid;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = 0;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
// Transition core 0 to P0 and wait for change to complete
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
PciAddress.Address.Register = CPTC0_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// warm reset request
FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
Request.RequestBit = TRUE;
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
} else {
// warm reset path
FunctionData.NewNbVid = NewNbVid;
FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
TaskPtr.DataTransfer.DataPtr = &FunctionData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
} // skip whole algorithm
}
