Esempio n. 1
0
static WRITE_HANDLER( parodius_052109_053245_w )
{
	if (videobank & 0x02)
		K053245_w(offset,data);
	else
		K052109_w(offset,data);
}
Esempio n. 2
0
static WRITE_HANDLER( bankedram_w )
{
	if (videobank & 0x02)
	{
		if (videobank & 0x04)
			paletteram_xBBBBBGGGGGRRRRR_swap_w(offset + 0x0800,data);
		else
			paletteram_xBBBBBGGGGGRRRRR_swap_w(offset,data);
	}
	else if (videobank & 0x01)
		K053245_w(offset,data);
	else
		ram[offset] = data;
}
Esempio n. 3
0
static WRITE8_HANDLER( le_4800_w )
{
	if (cur_control2 & 0x10)	/* RAM enable */
	{
		paletteram_xBBBBBGGGGGRRRRR_swap_w(offset,data);
	}
	else
	{
		if (offset < 0x0800)
		{
			switch (offset)
			{
				case 0xc6:
					sound_cmd_w(0, data);
					break;

				case 0xc7:
					sound_irq_w(0, data);
					break;

				case 0x40:
				case 0x41:
				case 0x42:
				case 0x43:
				case 0x44:
				case 0x45:
				case 0x46:
					K053244_w(offset-0x40, data);
					break;

				case 0x80:
				case 0x81:
				case 0x82:
				case 0x83:
				case 0x84:
				case 0x85:
				case 0x86:
				case 0x87:
				case 0x88:
				case 0x89:
				case 0x8a:
				case 0x8b:
				case 0x8c:
				case 0x8d:
				case 0x8e:
				case 0x8f:
				case 0x90:
				case 0x91:
				case 0x92:
				case 0x93:
				case 0x94:
				case 0x95:
				case 0x96:
				case 0x97:
				case 0x98:
				case 0x99:
				case 0x9a:
				case 0x9b:
				case 0x9c:
				case 0x9d:
				case 0x9e:
				case 0x9f:
					K054000_w(offset-0x80, data);
					break;

				default:
					logerror("Unknown LE 48xx register write: %x to %x (PC=%x)\n", data, offset, activecpu_get_pc());
					break;
			}
		}
		else if (offset < 0x1800)
		{
			K053245_w((offset - 0x0800) & 0x07ff, data);

		}
		else if (offset < 0x2000)
			K056832_ram_code_lo_w(offset - 0x1800, data);
		else if (offset < 0x2800)
			K056832_ram_code_hi_w(offset - 0x2000, data);
		else if (offset < 0x3000)
			K056832_ram_attr_lo_w(offset - 0x2800, data);
		else /* (offset < 0x3800) */
			K056832_ram_attr_hi_w(offset - 0x3000, data);
	}
}