static int
ks8695p_write_config_word(struct pci_dev *dev, int where, u16 value)
{
u32 reg, shift;
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
shift = where & 0x00000002;
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
reg = KS8695_READ(KS8695_2104);
switch (shift) {
case 2:
reg &= 0x0000ffff;
reg |= (u32)value << 16;
break;
default:
reg &= 0xffff0000;
reg |= (u32)value;
break;
}
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
KS8695_WRITE(KS8695_2104, reg);
return PCIBIOS_SUCCESSFUL;
}
void __init ks8695p_configure_interrupt(void)
{
u32 uReg;
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
uReg = KS8695_READ(KS8695_GPIO_MODE);
uReg |= 0x00000001; /* set it to output first */
KS8695_WRITE(KS8695_GPIO_MODE, uReg);
uReg = KS8695_READ(KS8695_GPIO_CTRL);
uReg &= 0xfffffff8; /* EXT0 is used as PCI bus interrupt source */
/* level detection (active low) */
uReg |= 0x8;
KS8695_WRITE(KS8695_GPIO_CTRL, uReg);
uReg = KS8695_READ(KS8695_GPIO_MODE);
uReg &= ~0x00000001; /* reset it to input first */
KS8695_WRITE(KS8695_GPIO_MODE, uReg);
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: OK\n", __FUNCTION__);
#endif
}
static int
ks8695p_write_config_dword(struct pci_dev *dev, int where, u32 value)
{
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
KS8695_WRITE(KS8695_2104, value);
return PCIBIOS_SUCCESSFUL;
}
void __init ks8695p_init(void *sysdata)
{
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
/* note that we need a stage 1 initialization in .S file to set 0x202c,
* before the stage 2 initialization here
*/
KS8695_WRITE(KS8695_202C, 0x00010001); /* stage 1 initialization, subid, subdevice = 0x0001 */
/* stage 2 initialization */
KS8695_WRITE(KS8695_2204, 0x40000000); /* prefetch limits with 16 words, retru enable */
/* configure memory mapping */
KS8695_WRITE(KS8695_2208, KS8695P_PCIBG_MEM_BASE);
//KS8695_WRITE(KS8695_220C, PMBAC_TRANS_ENABLE); /* enable memory address translation */
KS8695_WRITE(KS8695_2210, KS8695P_PCI_MEM_MASK); /* mask bits */
KS8695_WRITE(KS8695_2214, KS8695P_PCI_MEM_BASE); /* physical memory address */
/* configure IO mapping */
KS8695_WRITE(KS8695_2218, KS8695P_PCIBG_IO_BASE);
//KS8695_WRITE(KS8695_221C, PMBAC_TRANS_ENABLE); /* enable IO address translation */
KS8695_WRITE(KS8695_2220, KS8695P_PCI_IO_MASK); /* mask bits */
KS8695_WRITE(KS8695_2224, KS8695P_PCI_IO_BASE);
ks8695p_configure_interrupt();
pci_scan_bus(0, &ks8695p_ops, sysdata);
}
static int
ks8695p_read_config_dword(struct pci_dev *dev, int where, u32 *value)
{
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
*value = KS8695_READ(KS8695_2104);
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: value=0x%08x\n", __FUNCTION__, *value);
#endif
return PCIBIOS_SUCCESSFUL;
}
static int
ks8695p_read_config_word(struct pci_dev *dev, int where, u16 *value)
{
u32 reg, shift;
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
shift = where & 0x00000002;
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
reg = KS8695_READ(KS8695_2104);
*value = (u16)(reg >> (shift * 8));
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: value=0x%04x\n", __FUNCTION__, *value);
#endif
return PCIBIOS_SUCCESSFUL;
}
void __init ks8695p_init(void *sysdata)
{
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
#if defined(CONFIG_MACH_CM4008) || defined(CONFIG_MACH_CM41xx)
/* Enable PCI reset line as output */
*((volatile unsigned int *) (IO_ADDRESS(KS8695_IO_BASE) + KS8695_GPIO_MODE)) |= 0x2;
*((volatile unsigned int *) (IO_ADDRESS(KS8695_IO_BASE) + KS8695_GPIO_DATA)) &= ~0x2;
udelay(10000);
*((volatile unsigned int *) (IO_ADDRESS(KS8695_IO_BASE) + KS8695_GPIO_DATA)) |= 0x2;
#endif
/* note that we need a stage 1 initialization in .S file to set 0x202c,
* before the stage 2 initialization here
*/
KS8695_WRITE(KS8695_202C, 0x00010001); /* stage 1 initialization, subid, subdevice = 0x0001 */
/* stage 2 initialization */
KS8695_WRITE(KS8695_2204, 0x40000000); /* prefetch limits with 16 words, retru enable */
/* configure memory mapping */
KS8695_WRITE(KS8695_2208, KS8695P_PCIBG_MEM_BASE);
//KS8695_WRITE(KS8695_220C, PMBAC_TRANS_ENABLE); /* enable memory address translation */
KS8695_WRITE(KS8695_2210, KS8695P_PCI_MEM_MASK); /* mask bits */
KS8695_WRITE(KS8695_2214, KS8695P_PCI_MEM_BASE); /* physical memory address */
/* configure IO mapping */
KS8695_WRITE(KS8695_2218, KS8695P_PCIBG_IO_BASE);
//KS8695_WRITE(KS8695_221C, PMBAC_TRANS_ENABLE); /* enable IO address translation */
KS8695_WRITE(KS8695_2220, KS8695P_PCI_IO_MASK); /* mask bits */
KS8695_WRITE(KS8695_2224, KS8695P_PCI_IO_BASE);
ks8695p_configure_interrupt();
pci_scan_bus(0, &ks8695p_ops, sysdata);
}
static int
ks8695p_read_config_byte(struct pci_dev *dev, int where, u8 *value)
{
u32 reg, shift;
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: bus=%d\n", __FUNCTION__, dev->bus->number);
#endif
/*RLQ, actually there is not need to do shift since the caller will guarantee alignment */
shift = where & 0x00000003;
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
reg = KS8695_READ(KS8695_2104);
*value = (u8)(reg >> (shift * 8));
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: value=0x%02x\n", __FUNCTION__, *value);
#endif
return PCIBIOS_SUCCESSFUL;
}
