/**
* @brief Return SDMMCx clock frequency
* @param SDMMCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
* @retval SDMMC clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
*/
uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
{
uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
/* SDMMC1CLK clock frequency */
switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
{
case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */
if (LL_RCC_PLLSAI1_IsReady())
{
sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
}
break;
case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */
if (LL_RCC_PLL_IsReady())
{
sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
}
break;
case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */
if (LL_RCC_MSI_IsReady())
{
sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
(LL_RCC_MSI_IsEnabledRangeSelect() ?
LL_RCC_MSI_GetRange() :
LL_RCC_MSI_GetRangeAfterStandby()));
}
break;
case LL_RCC_SDMMC1_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */
default:
sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
break;
}
return sdmmc_frequency;
}
/**
* @brief Return SDMMCx clock frequency
* @param SDMMCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
* @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
*
* (*) value not defined in all devices.
* @retval SDMMC clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready
*/
uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
{
uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
{
/* SDMMC1CLK clock frequency */
switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
{
case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */
switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
{
case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
if (LL_RCC_PLL_IsReady())
{
sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
}
break;
case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
default:
if (LL_RCC_PLLSAI_IsReady())
{
sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
}
break;
}
break;
case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */
default:
sdmmc_frequency = RCC_GetSystemClockFreq();
break;
}
}
#if defined(SDMMC2)
else
{
/* SDMMC2CLK clock frequency */
switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
{
case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */
switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
{
case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
if (LL_RCC_PLL_IsReady())
{
sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
}
break;
case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
default:
if (LL_RCC_PLLSAI_IsReady())
{
sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
}
break;
}
break;
case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */
default:
sdmmc_frequency = RCC_GetSystemClockFreq();
break;
}
}
#endif /* SDMMC2 */
return sdmmc_frequency;
}
