/** * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source * - HSE, HSI, PLL and PLLSAIxSource OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval An ErrorStatus enumeration value: * - SUCCESS: RCC registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_RCC_DeInit(void) { uint32_t vl_mask = 0; /* Set MSION bit */ LL_RCC_MSI_Enable(); /* Insure MSIRDY bit is set before writing default MSIRANGE value */ while (LL_RCC_MSI_IsReady() == 0) { __NOP(); } /* Set MSIRANGE default value */ LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6); /* Set MSITRIM bits to the reset value*/ LL_RCC_MSI_SetCalibTrimming(0); /* Set HSITRIM bits to the reset value*/ LL_RCC_HSI_SetCalibTrimming(0x10); /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000); vl_mask = 0xFFFFFFFFU; /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */ CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON)); /* Reset PLLSAI1ON bit */ CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON); #if defined(RCC_PLLSAI2_SUPPORT) /* Reset PLLSAI2ON bit */ CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON); #endif /*RCC_PLLSAI2_SUPPORT*/ /* Write new mask in CR register */ LL_RCC_WriteReg(CR, vl_mask); /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 16 << RCC_POSITION_PLLN); /* Reset PLLSAI1CFGR register */ LL_RCC_WriteReg(PLLSAI1CFGR, 16 << RCC_POSITION_PLLSAI1N); #if defined(RCC_PLLSAI2_SUPPORT) /* Reset PLLSAI2CFGR register */ LL_RCC_WriteReg(PLLSAI2CFGR, 16 << RCC_POSITION_PLLSAI2N); #endif /*RCC_PLLSAI2_SUPPORT*/ /* Reset HSEBYP bit */ LL_RCC_HSE_DisableBypass(); /* Disable all interrupts */ LL_RCC_WriteReg(CIER, 0x00000000); return SUCCESS; }
/** * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE and PLL OFF * - AHB and APB1 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval An ErrorStatus enumeration value: * - SUCCESS: RCC registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_RCC_DeInit(void) { uint32_t vl_mask = 0U; /* Set HSION bit */ LL_RCC_HSI_Enable(); /* Set HSITRIM bits to the reset value*/ LL_RCC_HSI_SetCalibTrimming(0x10U); /* Reset SW, HPRE, PPRE and MCOSEL bits */ vl_mask = 0xFFFFFFFFU; CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL)); LL_RCC_WriteReg(CFGR, vl_mask); /* Reset HSEON, CSSON, PLLON bits */ vl_mask = 0xFFFFFFFFU; CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); LL_RCC_WriteReg(CR, vl_mask); /* Reset HSEBYP bit */ LL_RCC_HSE_DisableBypass(); /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); #if defined(RCC_HSI48_SUPPORT) /* Reset CR2 register */ LL_RCC_WriteReg(CR2, 0x00000000U); /* Disable HSI48 */ LL_RCC_HSI48_Disable(); #endif /*RCC_HSI48_SUPPORT*/ /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/ LL_RCC_HSI14_SetCalibTrimming(0x10U); LL_RCC_HSI14_Disable(); LL_RCC_HSI14_EnableADCControl(); /* Reset CFGR2 register */ LL_RCC_WriteReg(CFGR2, 0x00000000U); /* Reset CFGR3 register */ LL_RCC_WriteReg(CFGR3, 0x00000000U); /* Clear pending flags */ #if defined(RCC_HSI48_SUPPORT) vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC); #else vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC); #endif /* RCC_HSI48_SUPPORT */ SET_BIT(RCC->CIR, vl_mask); /* Disable all interrupts */ LL_RCC_WriteReg(CIR, 0x00000000U); return SUCCESS; }
/** * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source * - HSE, HSI and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval An ErrorStatus enumeration value: * - SUCCESS: RCC registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_RCC_DeInit(void) { uint32_t vl_mask = 0U; /* Set MSION bit */ LL_RCC_MSI_Enable(); /* Insure MSIRDY bit is set before writing default MSIRANGE value */ while (LL_RCC_MSI_IsReady() == 0U) { __NOP(); } /* Set MSIRANGE default value */ LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5); /* Set MSITRIM bits to the reset value*/ LL_RCC_MSI_SetCalibTrimming(0U); /* Set HSITRIM bits to the reset value*/ LL_RCC_HSI_SetCalibTrimming(0x10U); /* Reset SW, HPRE, PPRE and MCOSEL bits */ vl_mask = 0xFFFFFFFFU; CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL)); LL_RCC_WriteReg(CFGR, vl_mask); /* Reset HSI, HSE, PLL */ vl_mask = LL_RCC_ReadReg(CR); #if defined(RCC_CR_HSIOUTEN) CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ RCC_CR_HSEON | RCC_CR_PLLON); #else CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ RCC_CR_HSEON | RCC_CR_PLLON); #endif LL_RCC_WriteReg(CR, vl_mask); /* Delay after an RCC peripheral clock */ vl_mask = LL_RCC_ReadReg(CR); /* Reset HSEBYP bit */ LL_RCC_HSE_DisableBypass(); /* Set RCC_CR_RTCPRE to 0b00*/ CLEAR_BIT(vl_mask, RCC_CR_RTCPRE); LL_RCC_WriteReg(CR, vl_mask); /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); #if defined(RCC_HSI48_SUPPORT) /* Reset CRRCR register */ LL_RCC_WriteReg(CRRCR, 0x00000000U); /* Disable HSI48 */ LL_RCC_HSI48_Disable(); #endif /*RCC_HSI48_SUPPORT*/ /* Disable all interrupts */ LL_RCC_WriteReg(CIER, 0x00000000U); return SUCCESS; }
static int stm32_clock_control_init(struct device *dev) { LL_UTILS_ClkInitTypeDef s_ClkInitStruct; ARG_UNUSED(dev); /* configure clock for AHB/APB buses */ config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct); /* Some clocks would be activated by default */ config_enable_default_clocks(); #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL LL_UTILS_PLLInitTypeDef s_PLLInitStruct; /* configure PLL input settings */ config_pll_init(&s_PLLInitStruct); /* * Switch to HSI and disable the PLL before configuration. * (Switching to HSI makes sure we have a SYSCLK source in * case we're currently running from the PLL we're about to * turn off and reconfigure.) * * Don't use s_ClkInitStruct.AHBCLKDivider as the AHB * prescaler here. In this configuration, that's the value to * use when the SYSCLK source is the PLL, not HSI. */ stm32_clock_switch_to_hsi(LL_RCC_SYSCLK_DIV_1); LL_RCC_PLL_Disable(); #ifdef CONFIG_CLOCK_STM32_PLL_Q_DIVISOR MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, CONFIG_CLOCK_STM32_PLL_Q_DIVISOR << POSITION_VAL(RCC_PLLCFGR_PLLQ)); #endif /* CONFIG_CLOCK_STM32_PLL_Q_DIVISOR */ #ifdef CONFIG_CLOCK_STM32_PLL_SRC_MSI /* Switch to PLL with MSI as clock source */ LL_PLL_ConfigSystemClock_MSI(&s_PLLInitStruct, &s_ClkInitStruct); /* Disable other clocks */ LL_RCC_HSI_Disable(); LL_RCC_HSE_Disable(); #elif CONFIG_CLOCK_STM32_PLL_SRC_HSI /* Switch to PLL with HSI as clock source */ LL_PLL_ConfigSystemClock_HSI(&s_PLLInitStruct, &s_ClkInitStruct); /* Disable other clocks */ LL_RCC_HSE_Disable(); LL_RCC_MSI_Disable(); #elif CONFIG_CLOCK_STM32_PLL_SRC_HSE int hse_bypass = LL_UTILS_HSEBYPASS_OFF; #ifdef CONFIG_CLOCK_STM32_HSE_BYPASS hse_bypass = LL_UTILS_HSEBYPASS_ON; #endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */ /* Switch to PLL with HSE as clock source */ LL_PLL_ConfigSystemClock_HSE(CONFIG_CLOCK_STM32_HSE_CLOCK, hse_bypass, &s_PLLInitStruct, &s_ClkInitStruct); /* Disable other clocks */ LL_RCC_HSI_Disable(); LL_RCC_MSI_Disable(); #endif /* CONFIG_CLOCK_STM32_PLL_SRC_... */ #elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE /* Enable HSE if not enabled */ if (LL_RCC_HSE_IsReady() != 1) { /* Check if need to enable HSE bypass feature or not */ #ifdef CONFIG_CLOCK_STM32_HSE_BYPASS LL_RCC_HSE_EnableBypass(); #else LL_RCC_HSE_DisableBypass(); #endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */ /* Enable HSE */ LL_RCC_HSE_Enable(); while (LL_RCC_HSE_IsReady() != 1) { /* Wait for HSE ready */ } } /* Set HSE as SYSCLCK source */ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE); LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider); while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) { } /* Update SystemCoreClock variable */ LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ( CONFIG_CLOCK_STM32_HSE_CLOCK, s_ClkInitStruct.AHBCLKDivider)); /* Set APB1 & APB2 prescaler*/ LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); #ifndef CONFIG_SOC_SERIES_STM32F0X LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); #endif /* CONFIG_SOC_SERIES_STM32F0X */ /* Set flash latency */ /* HSI used as SYSCLK, set latency to 0 */ LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); /* Disable other clocks */ LL_RCC_HSI_Disable(); LL_RCC_MSI_Disable(); LL_RCC_PLL_Disable(); #elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI stm32_clock_switch_to_hsi(s_ClkInitStruct.AHBCLKDivider); /* Update SystemCoreClock variable */ LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(HSI_VALUE, s_ClkInitStruct.AHBCLKDivider)); /* Set APB1 & APB2 prescaler*/ LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); #ifndef CONFIG_SOC_SERIES_STM32F0X LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); #endif /* CONFIG_SOC_SERIES_STM32F0X */ /* Set flash latency */ /* HSI used as SYSCLK, set latency to 0 */ LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); /* Disable other clocks */ LL_RCC_HSE_Disable(); LL_RCC_MSI_Disable(); LL_RCC_PLL_Disable(); #endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_... */ return 0; }