/** * @brief Return PLL clock frequency used for system domain * @retval PLL clock frequency (in Hz) */ uint32_t RCC_PLL_GetFreqDomain_SYS(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ /* Get PLL source */ pllsource = LL_RCC_PLL_GetMainSource(); switch (pllsource) { case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllinputfreq = HSE_VALUE; break; default: pllinputfreq = HSI_VALUE; break; } return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider()); }
/** * @brief Return PLL clock frequency used for system domain * @retval PLL clock frequency (in Hz) */ uint32_t RCC_PLL_GetFreqDomain_SYS(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ /* Get PLL source */ pllsource = LL_RCC_PLL_GetMainSource(); switch (pllsource) { #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; #else case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE / 2; #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ break; #if defined(RCC_CFGR_SW_HSI48) case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ pllinputfreq = HSI48_VALUE; break; #endif /* RCC_CFGR_SW_HSI48 */ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllinputfreq = HSE_VALUE; break; default: #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) pllinputfreq = HSI_VALUE; #else pllinputfreq = HSI_VALUE / 2; #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ break; } #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv()); #else return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator()); #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ }