static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) { int i; for (i = 0; i < LPAIF_I2S_PORT_NUM; ++i) if (reg == LPAIF_I2SCTL_REG(i)) return true; for (i = 0; i < LPAIF_IRQ_PORT_NUM; ++i) { if (reg == LPAIF_IRQEN_REG(i)) return true; if (reg == LPAIF_IRQSTAT_REG(i)) return true; } for (i = 0; i < LPAIF_RDMA_CHAN_NUM; ++i) { if (reg == LPAIF_RDMACTL_REG(i)) return true; if (reg == LPAIF_RDMABASE_REG(i)) return true; if (reg == LPAIF_RDMABUFF_REG(i)) return true; if (reg == LPAIF_RDMACURR_REG(i)) return true; if (reg == LPAIF_RDMAPER_REG(i)) return true; } return false; }
static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) { struct lpass_data *drvdata = dev_get_drvdata(dev); struct lpass_variant *v = drvdata->variant; int i; for (i = 0; i < v->i2s_ports; ++i) if (reg == LPAIF_I2SCTL_REG(v, i)) return true; for (i = 0; i < v->irq_ports; ++i) { if (reg == LPAIF_IRQEN_REG(v, i)) return true; if (reg == LPAIF_IRQSTAT_REG(v, i)) return true; } for (i = 0; i < v->rdma_channels; ++i) { if (reg == LPAIF_RDMACTL_REG(v, i)) return true; if (reg == LPAIF_RDMABASE_REG(v, i)) return true; if (reg == LPAIF_RDMABUFF_REG(v, i)) return true; if (reg == LPAIF_RDMACURR_REG(v, i)) return true; if (reg == LPAIF_RDMAPER_REG(v, i)) return true; } return false; }
static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; struct lpass_data *drvdata = snd_soc_platform_get_drvdata(soc_runtime->platform); int ret; ret = regmap_write(drvdata->lpaif_map, LPAIF_RDMABASE_REG(LPAIF_RDMA_CHAN_MI2S), runtime->dma_addr); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n", __func__, ret); return ret; } ret = regmap_write(drvdata->lpaif_map, LPAIF_RDMABUFF_REG(LPAIF_RDMA_CHAN_MI2S), (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n", __func__, ret); return ret; } ret = regmap_write(drvdata->lpaif_map, LPAIF_RDMAPER_REG(LPAIF_RDMA_CHAN_MI2S), (snd_pcm_lib_period_bytes(substream) >> 2) - 1); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n", __func__, ret); return ret; } ret = regmap_update_bits(drvdata->lpaif_map, LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), LPAIF_RDMACTL_ENABLE_MASK, LPAIF_RDMACTL_ENABLE_ON); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", __func__, ret); return ret; } return 0; }
for (i = 0; i < LPAIF_IRQ_PORT_NUM; ++i) if (reg == LPAIF_IRQSTAT_REG(i)) return true; for (i = 0; i < LPAIF_RDMA_CHAN_NUM; ++i) if (reg == LPAIF_RDMACURR_REG(i)) return true; return false; } static const struct regmap_config lpass_cpu_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = LPAIF_RDMAPER_REG(LPAIF_RDMA_CHAN_MAX), .writeable_reg = lpass_cpu_regmap_writeable, .readable_reg = lpass_cpu_regmap_readable, .volatile_reg = lpass_cpu_regmap_volatile, .cache_type = REGCACHE_FLAT, }; static int lpass_cpu_platform_probe(struct platform_device *pdev) { struct lpass_data *drvdata; struct device_node *dsp_of_node; struct resource *res; int ret; dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); if (dsp_of_node) {
int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) { struct lpass_data *drvdata; struct device_node *dsp_of_node; struct resource *res; struct lpass_variant *variant; struct device *dev = &pdev->dev; const struct of_device_id *match; char clk_name[16]; int ret, i, dai_id; dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); if (dsp_of_node) { dev_err(&pdev->dev, "%s() DSP exists and holds audio resources\n", __func__); return -EBUSY; } drvdata = devm_kzalloc(&pdev->dev, sizeof(struct lpass_data), GFP_KERNEL); if (!drvdata) return -ENOMEM; platform_set_drvdata(pdev, drvdata); match = of_match_device(dev->driver->of_match_table, dev); if (!match || !match->data) return -EINVAL; drvdata->variant = (struct lpass_variant *)match->data; variant = drvdata->variant; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif"); drvdata->lpaif = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR((void const __force *)drvdata->lpaif)) { dev_err(&pdev->dev, "%s() error mapping reg resource: %ld\n", __func__, PTR_ERR((void const __force *)drvdata->lpaif)); return PTR_ERR((void const __force *)drvdata->lpaif); } lpass_cpu_regmap_config.max_register = LPAIF_RDMAPER_REG(variant, variant->rdma_channels); drvdata->lpaif_map = devm_regmap_init_mmio(&pdev->dev, drvdata->lpaif, &lpass_cpu_regmap_config); if (IS_ERR(drvdata->lpaif_map)) { dev_err(&pdev->dev, "%s() error initializing regmap: %ld\n", __func__, PTR_ERR(drvdata->lpaif_map)); return PTR_ERR(drvdata->lpaif_map); } if (variant->init) variant->init(pdev); for (i = 0; i < variant->num_dai; i++) { dai_id = variant->dai_driver[i].id; if (variant->num_dai > 1) sprintf(clk_name, "mi2s-osr-clk%d", i); else sprintf(clk_name, "mi2s-osr-clk"); drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(&pdev->dev, clk_name); if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) { dev_warn(&pdev->dev, "%s() error getting mi2s-osr-clk: %ld\n", __func__, PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); } if (variant->num_dai > 1) sprintf(clk_name, "mi2s-bit-clk%d", i); else sprintf(clk_name, "mi2s-bit-clk"); drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(&pdev->dev, clk_name); if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { dev_err(&pdev->dev, "%s() error getting mi2s-bit-clk: %ld\n", __func__, PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); } } drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk"); if (IS_ERR(drvdata->ahbix_clk)) { dev_err(&pdev->dev, "%s() error getting ahbix-clk: %ld\n", __func__, PTR_ERR(drvdata->ahbix_clk)); return PTR_ERR(drvdata->ahbix_clk); } ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY); if (ret) { dev_err(&pdev->dev, "%s() error setting rate on ahbix_clk: %d\n", __func__, ret); return ret; } dev_dbg(&pdev->dev, "%s() set ahbix_clk rate to %lu\n", __func__, clk_get_rate(drvdata->ahbix_clk)); ret = clk_prepare_enable(drvdata->ahbix_clk); if (ret) { dev_err(&pdev->dev, "%s() error enabling ahbix_clk: %d\n", __func__, ret); return ret; } ret = devm_snd_soc_register_component(&pdev->dev, &lpass_cpu_comp_driver, variant->dai_driver, variant->num_dai); if (ret) { dev_err(&pdev->dev, "%s() error registering cpu driver: %d\n", __func__, ret); goto err_clk; } ret = asoc_qcom_lpass_platform_register(pdev); if (ret) { dev_err(&pdev->dev, "%s() error registering platform driver: %d\n", __func__, ret); goto err_clk; } return 0; err_clk: clk_disable_unprepare(drvdata->ahbix_clk); return ret; }