* Pin configuration table for Hitex LPC1850 Eval, it is compatible to LPC4350.
*
* This table does not list all MCU pins that will be configured. See also
* the code in `iomux_init()`.
*/
static const struct lpc18xx_pin_config hitex_lpc4350_iomux[] = {
/*
* Pin configuration for UART
*/
// shlee2302 130506 : uart setting
//{{CONFIG_LPC18XX_UART_TX_IO_GROUP, CONFIG_LPC18XX_UART_TX_IO_PIN},
// LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 0, 0)},
//{{CONFIG_LPC18XX_UART_RX_IO_GROUP, CONFIG_LPC18XX_UART_RX_IO_PIN},
// LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 1, 0)},
{{CONFIG_LPC18XX_UART_TX_IO_GROUP, CONFIG_LPC18XX_UART_TX_IO_PIN},
LPC18XX_IOMUX_CONFIG(CONFIG_LPC18XX_UART_TX_IO_FUNC, 0, 1, 0, 0, 0)},
{{CONFIG_LPC18XX_UART_RX_IO_GROUP, CONFIG_LPC18XX_UART_RX_IO_PIN},
LPC18XX_IOMUX_CONFIG(CONFIG_LPC18XX_UART_RX_IO_FUNC, 0, 1, 0, 1, 0)},
#ifdef CONFIG_LPC18XX_ETH
/*
* Pin configuration for Ethernet (MII + MDIO)
*/
#if 0 // shlee2302 130506
/* PC.1 = ENET_MDC */
{{0xC, 1}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.17 = ENET_MDIO (high-drive pin) */
{{0x1, 17}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.18 = ENET_TXD0 */
{{0x1, 18}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.20 = ENET_TXD1 */
LPC18XX_EMC_BASE)
DECLARE_GLOBAL_DATA_PTR;
/*
* Pin configuration table for Hitex LPC4350 Eval.
*
* This table does not list all MCU pins that will be configured. See also
* the code in `iomux_init()`.
*/
static const struct lpc18xx_pin_config hitex_lpc4350_iomux[] = {
/*
* Pin configuration for UART
*/
{{CONFIG_LPC18XX_UART_TX_IO_GROUP, CONFIG_LPC18XX_UART_TX_IO_PIN},
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 0, 0)},
{{CONFIG_LPC18XX_UART_RX_IO_GROUP, CONFIG_LPC18XX_UART_RX_IO_PIN},
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 1, 0)},
#ifdef CONFIG_LPC18XX_ETH
/*
* Pin configuration for Ethernet (MII + MDIO)
*/
/* PC.1 = ENET_MDC */
{{0xC, 1}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.17 = ENET_MDIO (high-drive pin) */
{{0x1, 17}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.18 = ENET_TXD0 */
{{0x1, 18}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.20 = ENET_TXD1 */
{{0x1, 20}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/*
* Set up IOMUX configuration of the various processor chips
*/
void __init lpc18xx_iomux_init(void)
{
int p = lpc18xx_platform_get();
if (p == PLATFORM_LPC18XX_HITEX_LPC4350_EVAL) {
#if defined(CONFIG_LPC18XX_SPI0)
/*
* Tie the SPI Flash of Hitex EVAL LPC4350 to SSP0.
* Note that CS is defined as a software-driven GPIO.
*/
lpc18xx_pin_config(0x3, 3, LPC18XX_IOMUX_CONFIG_CLOCK(2));
lpc18xx_pin_config(0x3, 6, LPC18XX_IOMUX_CONFIG_IN(5));
lpc18xx_pin_config(0x3, 7, LPC18XX_IOMUX_CONFIG_OUT(5));
lpc18xx_pin_config(0x3, 8, LPC18XX_IOMUX_CONFIG_OUT(4));
#endif
#if defined(CONFIG_LPC18XX_I2C0)
writel(LPC18XX_SFSI2C0_CONFIG, LPC18XX_SFSI2C0);
#endif
#if defined(CONFIG_LPC18XX_I2C1)
/*
* Configure I2C1 pins I2C1_SDA and I2C1_SCL: setup EHS, EZI,
* ZIF bits (refer to section 15.4.1 of UM)
*/
lpc18xx_pin_config(0xE, 13,
LPC18XX_IOMUX_CONFIG(2, 0, 0, 1, 1, 1));
lpc18xx_pin_config(0xE, 15,
LPC18XX_IOMUX_CONFIG(2, 0, 0, 1, 1, 1));
#endif
#if defined(CONFIG_LPC18XX_MMC)
/* LPC18XX_IOMUX_CONFIG(func,epldwn,neplup,ehighslew,einput,glitchfilter) */
/* PC_0 - SDIO_CLK */
lpc18xx_pin_config(0xC, 0,
LPC18XX_IOMUX_CONFIG(7, 0, 1, 1, 1, 1));
/* PC_1 - SDIO_VOLT0 */
// lpc18xx_pin_config(0xC, 1,
// LPC18XX_IOMUX_CONFIG(7, 0, 0, 1, 0, 1));
/* PC_2 - SDIO_RST (?) */
lpc18xx_pin_config(0xC, 2,
LPC18XX_IOMUX_CONFIG(7, 0, 1, 1, 0, 1));
/* PC_3 - SDIO_VOLT1 */
//lpc18xx_pin_config(0xC, 3,
// LPC18XX_IOMUX_CONFIG(7, 0, 0, 1, 0, 1));
/* PC_4 - SDIO_D0 */
lpc18xx_pin_config(0xC, 4,
LPC18XX_IOMUX_CONFIG(7, 0, 1, 1, 1, 1));
/* PC_5 - SDIO_D1 */
lpc18xx_pin_config(0xC, 5,
LPC18XX_IOMUX_CONFIG(7, 0, 1, 1, 1, 1));
/* PC_6 - SDIO_D2 */
lpc18xx_pin_config(0xC, 6,
LPC18XX_IOMUX_CONFIG(7, 0, 1, 1, 1, 1));
/* PC_7 - SDIO_D3 */
lpc18xx_pin_config(0xC, 7,
LPC18XX_IOMUX_CONFIG(7, 0, 1, 1, 1, 1));
/* PC_8 - SDIO_CD */
lpc18xx_pin_config(0xC, 8,
LPC18XX_IOMUX_CONFIG(7, 0, 1, 0, 1, 0));
/* PC_10 - SDIO_CMD */
lpc18xx_pin_config(0xC, 10,
LPC18XX_IOMUX_CONFIG(7, 0, 1, 1, 1, 1));
/* PD_1 - SDIO_POW */
lpc18xx_pin_config(0xD, 1,
LPC18XX_IOMUX_CONFIG(5, 0, 1, 0, 0, 0));
#endif /* CONFIG_LPC18XX_MMC */
}
else if (p == PLATFORM_LPC18XX_EA_LPC4357_EVAL) {
#if defined (CONFIG_FB_ARMCLCD) || defined(CONFIG_MTD_M25P80_SPIFI)
int i;
#endif
#if defined(CONFIG_GPIOLIB) && defined(CONFIG_GPIO_SYSFS)
/* 5-key joystick (SW7) */
/* GPIO4[8] */
lpc18xx_pin_config(0xA, 1, LPC18XX_IOMUX_CONFIG_IN(0));
#if 0
/* User Input */
/* GPIOTBD[TBD] */
lpc18xx_pin_config(0xTBD, TBD, LPC18XX_IOMUX_CONFIG_OUT(0));
#endif
#endif
#if defined (CONFIG_FB_ARMCLCD)
/* LCD interface */
static struct iomux_pin_config arm_clcd_iomux[] = {
/* RED0->4 */
{0x4, 2, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{0x8, 7, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{0x8, 6, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{0x8, 5, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{0x8, 4, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
/* GREEN0->5 */
{0x4, 10, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{0x4, 9, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{0x8, 3, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{0xB, 6, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{0xB, 5, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{0xB, 4, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
/* BLUE0->4 */
{0x7, 1, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
{0xB, 3, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{0xB, 2, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{0xB, 1, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
{0xB, 0, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
/* LCD_FP */
{0x4, 5, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
/* LCD_ENAB */
{0x4, 6, LPC18XX_IOMUX_CONFIG(2, 0, 1, 1, 1, 0)},
/* LCD_DCLK */
{0x4, 7, LPC18XX_IOMUX_CONFIG(0, 0, 1, 1, 1, 0)},
/* LCD_LE */
{0x7, 0, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
/* LCD_LP */
{0x7, 6, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
/* LCD_PWR */
{0x7, 7, LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 0)},
};
for (i = 0; i < ARRAY_SIZE(arm_clcd_iomux); i++) {
struct iomux_pin_config *p = &arm_clcd_iomux[i];
lpc18xx_pin_config(p->group, p->pin, p->mask);
}
#endif /* CONFIG_FB_ARMCLCD */
#if defined(CONFIG_LPC18XX_I2C0)
writel(LPC18XX_SFSI2C0_CONFIG, LPC18XX_SFSI2C0);
#endif
#if defined(CONFIG_LPC18XX_I2C1)
/*
* Configure I2C1 pins I2C1_SDA and I2C1_SCL: setup EHS, EZI,
* ZIF bits (refer to section 15.4.1 of UM)
*/
lpc18xx_pin_config(0x2, 3,
LPC18XX_IOMUX_CONFIG(1, 0, 0, 1, 1, 1));
lpc18xx_pin_config(0x2, 4,
LPC18XX_IOMUX_CONFIG(1, 0, 0, 1, 1, 1));
#endif
#if defined(CONFIG_MTD_M25P80_SPIFI)
/* Setup SPIFI pins */
for (i = 3; i <= 7; ++i) {
lpc18xx_pin_config(0x3, i,
LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 1, 1));
}
/* SSEL is output only */
lpc18xx_pin_config(0x3, 8,
LPC18XX_IOMUX_CONFIG(3, 0, 1, 1, 0, 0));
#endif
}
}
