/* Configure pin function */
void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)
{
if (port == PINMUX_CLK) {
LPC_SCU_CLK(((uint32_t) LPC_SCU), pin) = mode + func;
}
else {
LPC_SCU->SFSP[port][pin] = mode + func;
}
}
/*----------------------------------------------------------------------------
Initialize board specific IO
*----------------------------------------------------------------------------*/
void vIOInit(void)
{
uint32_t *conf;
// disable clocks to peripherals we don't use
LPC_CCU1->CLK_APB3_I2C1_CFG = 0;
LPC_CCU1->CLK_APB3_DAC_CFG = 0;
LPC_CCU1->CLK_APB3_ADC1_CFG = 0;
LPC_CCU1->CLK_APB3_CAN0_CFG = 0;
LPC_CCU1->CLK_APB1_MOTOCONPWM_CFG = 0;
LPC_CCU1->CLK_APB1_I2S_CFG = 0;
LPC_CCU1->CLK_APB1_CAN1_CFG = 0;
LPC_CCU1->CLK_M4_LCD_CFG = 0;
LPC_CCU1->CLK_M4_ETHERNET_CFG = 0;
LPC_CCU1->CLK_M4_EMC_CFG = 0;
LPC_CCU1->CLK_M4_SDIO_CFG = 0;
LPC_CCU1->CLK_M4_USB1_CFG = 0;
LPC_CCU1->CLK_M4_EMCDIV_CFG = 0;
LPC_CCU1->CLK_M4_USART2_CFG = 0;
LPC_CCU1->CLK_M4_USART3_CFG = 0;
LPC_CCU1->CLK_M4_SSP0_CFG = 0;
LPC_CCU1->CLK_M4_QEI_CFG = 0;
LPC_CCU1->CLK_PERIPH_SGPIO_CFG = 0;
LPC_CCU2->CLK_APB0_SSP0_CFG = 0;
LPC_CCU2->CLK_APB2_USART3_CFG = 0;
LPC_CCU2->CLK_APB2_USART2_CFG = 0;
LPC_CCU2->CLK_SDIO_CFG = 0;
// reset all pin configs
for (conf=(uint32_t *)0x40086000; conf<(uint32_t *)0x400867ac; conf++)
*conf = 0;
scu_pinmux(0x0, 0, (MD_PUP | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio0[0] siod
scu_pinmux(0x0, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio0[1] sioc
scu_pinmux(0x1, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio0[2] PWDN
scu_pinmux(0x1, 16, (MD_PUP | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio0[3] RSTB
scu_pinmux(0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[0] Y0
scu_pinmux(0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[1] Y1
scu_pinmux(0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[2] Y2
scu_pinmux(0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[3] Y3
scu_pinmux(0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[4] Y4
scu_pinmux(0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[5] Y5
scu_pinmux(0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[6] Y6
scu_pinmux(0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[7] Y7
scu_pinmux(0x1, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[8] Y8
scu_pinmux(0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[9] Y9
scu_pinmux(0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[11] HSYNC
scu_pinmux(0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[12] VSYNC
scu_pinmux(0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio1[13] PCLK
scu_pinmux(0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); // CTOUT_6 RCS0 CHANGED FROM FUNC1 TO FUNC0
scu_pinmux(0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); // CTOUT_7 RCS1
scu_pinmux(0x4, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); // CTOUT_0 RED ORIGINALLY FUNC1
scu_pinmux(0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); // CTOUT_1 GREEN ORIGINALLY FUNC1
scu_pinmux(0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); // CTOUT_2 BLUE ORIGINALLY FUNC1
scu_pinmux(0x3, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // gpio5[8] VBUS_EN
scu_pinmux(0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // U1_TXD (output)
scu_pinmux(0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // U1_RXD (input)
scu_pinmux(0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // U0_TXD
scu_pinmux(0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // U0_RXD
scu_pinmux(0x1, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC5); // SSP1_MISO
scu_pinmux(0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC5); // SSP1_MOSI
scu_pinmux(0x1, 19, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); // SSP1_SCK
scu_pinmux(0x1, 20, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); // SSP1_SSEL
scu_pinmux(0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // gpio5[2]
scu_pinmux(0x2, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // gpio5[3]
scu_pinmux(0x2, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // gpio5[4]
scu_pinmux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // gpio5[5] rev 1.1 SS control
scu_pinmux(0x3, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // gpio5[9]
scu_pinmux(0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC4); // push-button gpio5[7]
scu_pinmux(0x4, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio2[1] rev 1.1
//scu_pinmux(0x7, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio4[9]
//scu_pinmux(0x7, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio4[9]
//scu_pinmux(0x7, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio4[9]
//scu_pinmux(0x7, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0); // gpio4[9]
LPC_SCU_CLK(0) = 1 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* EXTBUS_CLK0 IDIVB input */
}
void MemoryPinInit(void)
{
/* select correct functions on the GPIOs */
#if 1
/* DATA LINES 0..31 > D0..D31 */
/* P1_7 - EXTBUS_D0 — External memory data line 0 */
scu_pinmux(0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_7: D0 (function 0) errata */
scu_pinmux(0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_8: D1 (function 0) errata */
scu_pinmux(0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_9: D2 (function 0) errata */
scu_pinmux(0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_10: D3 (function 0) errata */
scu_pinmux(0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_11: D4 (function 0) errata */
scu_pinmux(0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_12: D5 (function 0) errata */
scu_pinmux(0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_13: D6 (function 0) errata */
scu_pinmux(0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_14: D7 (function 0) errata */
scu_pinmux(0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_4: D8 (function 0) errata */
scu_pinmux(0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_5: D9 (function 0) errata */
scu_pinmux(0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_6: D10 (function 0) errata */
scu_pinmux(0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_7: D11 (function 0) errata */
scu_pinmux(0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_0: D12 (function 0) errata */
scu_pinmux(0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_1: D13 (function 0) errata */
scu_pinmux(0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_2: D14 (function 0) errata */
scu_pinmux(0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_3: D15 (function 0) errata */
#if 1
scu_pinmux(0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_2: D16 (function 0) errata */
scu_pinmux(0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_3: D17 (function 0) errata */
scu_pinmux(0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_4: D18 (function 0) errata */
scu_pinmux(0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_5: D19 (function 0) errata */
scu_pinmux(0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_6: D20 (function 0) errata */
scu_pinmux(0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_7: D21 (function 0) errata */
scu_pinmux(0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_8: D22 (function 0) errata */
scu_pinmux(0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_9: D23 (function 0) errata */
scu_pinmux(0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_5: D24 (function 0) errata */
scu_pinmux(0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_6: D25 (function 0) errata */
scu_pinmux(0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_7: D26 (function 0) errata */
scu_pinmux(0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_8: D27 (function 0) errata */
scu_pinmux(0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_9: D28 (function 0) errata */
scu_pinmux(0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_10: D29 (function 0) errata */
scu_pinmux(0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_11: D30 (function 0) errata */
scu_pinmux(0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_12: D31 (function 0) errata */
#endif
/* ADDRESS LINES A0..A11 > A0..A11 */
scu_pinmux(0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_9 - EXTBUS_A0 — External memory address line 0 */
scu_pinmux(0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_10 - EXTBUS_A1 — External memory address line 1 */
scu_pinmux(0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_11 - EXTBUS_A2 — External memory address line 2 */
scu_pinmux(0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_12 - EXTBUS_A3 — External memory address line 3 */
scu_pinmux(0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_13 - EXTBUS_A4 — External memory address line 4 */
scu_pinmux(0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_0 - EXTBUS_A5 — External memory address line 5 */
scu_pinmux(0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_1 - EXTBUS_A6 — External memory address line 6 */
scu_pinmux(0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_2 - EXTBUS_A7 — External memory address line 7 */
scu_pinmux(0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_8 - EXTBUS_A8 — External memory address line 8 */
scu_pinmux(0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_7 - EXTBUS_A9 — External memory address line 9 */
scu_pinmux(0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_6 - EXTBUS_A10 — External memory address line 10 */
scu_pinmux(0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_2 - EXTBUS_A11 — External memory address line 11 */
scu_pinmux(0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_1 - EXTBUS_A12 — External memory address line 12 */
scu_pinmux(0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_0 - EXTBUS_A13 — External memory address line 13 */
scu_pinmux(0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_8 - EXTBUS_A14 — External memory address line 14 */
scu_pinmux(0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_7 - EXTBUS_A15 — External memory address line 15 */
scu_pinmux(0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_16 - EXTBUS_A16 — External memory address line 16 */
scu_pinmux(0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_15 - EXTBUS_A17 — External memory address line 17 */
scu_pinmux(0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_0 - EXTBUS_A18 — External memory address line 18 */
scu_pinmux(0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_1 - EXTBUS_A19 — External memory address line 19 */
scu_pinmux(0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_2 - EXTBUS_A20 — External memory address line 20 */
scu_pinmux(0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_3 - EXTBUS_A21 — External memory address line 21 */
scu_pinmux(0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_4 - EXTBUS_A22 — External memory address line 22 */
scu_pinmux(0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PA_4 - EXTBUS_A23 — External memory address line 23 */
/* BYTE ENABLES */
scu_pinmux(0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_4 - EXTBUS_BLS0 — LOW active Byte Lane select signal 0 */
scu_pinmux(0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_6 - EXTBUS_BLS1 — LOW active Byte Lane select signal 1 */
scu_pinmux(0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_13 - EXTBUS_BLS2 — LOW active Byte Lane select signal 2 */
scu_pinmux(0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_10 - EXTBUS_BLS3 — LOW active Byte Lane select signal 3 */
scu_pinmux(0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_9: EXTBUS_DYCS0 (function 0) > CS# errata */
scu_pinmux(0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_6: WE (function 0) errata */
scu_pinmux(0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_4: CAS (function 0) > CAS# errata */
scu_pinmux(0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_5: RAS (function 0) > RAS# errata */
LPC_SCU_CLK(0) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK0: EXTBUS_CLK0 (function 0, from datasheet) > CLK ds */
LPC_SCU_CLK(1) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK1: EXTBUS_CLK1 (function 2, from datasheet) */
LPC_SCU_CLK(2) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK2: EXTBUS_CLK2 (function 2, from datasheet) */
LPC_SCU_CLK(3) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK3: EXTBUS_CLK3 (function 2, from datasheet) */
scu_pinmux(0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_11: CKEOUT0 (function 0) > CKE errata */
scu_pinmux(0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_12: DQMOUT0 (function 0) > DQM0 errata */
scu_pinmux(0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_10: DQMOUT1 (function 0) > DQM1 errata */
scu_pinmux(0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_0: DQMOUT2 (function 2, from datasheet) > DQM2 errata */
scu_pinmux(0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_13: DQMOUT3 (function 3, from datasheet) > DQM3 errata */
scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 ); //OE
scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 ); //BLS0
scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 ); //CS0
scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 ); //WE
#endif
}
/****************************************************************************************
* Set up the address/data pins for external memory interface in LP43xx
*
* Modify this function in case not all of the address/data pins are needed.
****************************************************************************************/
void EMC_Config_Pinmux(void)
{
// Disable the external memory controller before changing pin control configuration
LPC_EMC->CONTROL = 0x00000000;
// EMC_OUT (PUP_CLEAR | SLEWRATE_FAST | FILTER_DISABLE)
// EMC_IO (PUP_CLEAR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
// Data line configuration
scu_pinmux(0x1, 7, EMC_IO, FUNC3); // P1_7: D0
scu_pinmux(0x1, 8, EMC_IO, FUNC3); // P1_8: D1
scu_pinmux(0x1, 9, EMC_IO, FUNC3); // P1_9: D2
scu_pinmux(0x1, 10, EMC_IO, FUNC3); // P1_10: D3
scu_pinmux(0x1, 11, EMC_IO, FUNC3); // P1_11: D4
scu_pinmux(0x1, 12, EMC_IO, FUNC3); // P1_12: D5
scu_pinmux(0x1, 13, EMC_IO, FUNC3); // P1_13: D6
scu_pinmux(0x1, 14, EMC_IO, FUNC3); // P1_14: D7
scu_pinmux(0x5, 4, EMC_IO, FUNC2); // P5_4: D8
scu_pinmux(0x5, 5, EMC_IO, FUNC2); // P5_5: D9
scu_pinmux(0x5, 6, EMC_IO, FUNC2); // P5_6: D10
scu_pinmux(0x5, 7, EMC_IO, FUNC2); // P5_7: D11
scu_pinmux(0x5, 0, EMC_IO, FUNC2); // P5_0: D12
scu_pinmux(0x5, 1, EMC_IO, FUNC2); // P5_1: D13
scu_pinmux(0x5, 2, EMC_IO, FUNC2); // P5_2: D14
scu_pinmux(0x5, 3, EMC_IO, FUNC2); // P5_3: D15
scu_pinmux(0xD, 2, EMC_IO, FUNC2); // PD_2: D16
scu_pinmux(0xD, 3, EMC_IO, FUNC2); // PD_3: D17
scu_pinmux(0xD, 4, EMC_IO, FUNC2); // PD_4: D18
scu_pinmux(0xD, 5, EMC_IO, FUNC2); // PD_5: D19
scu_pinmux(0xD, 6, EMC_IO, FUNC2); // PD_6: D20
scu_pinmux(0xD, 7, EMC_IO, FUNC2); // PD_7: D21
scu_pinmux(0xD, 8, EMC_IO, FUNC2); // PD_8: D22
scu_pinmux(0xD, 9, EMC_IO, FUNC2); // PD_9: D23
scu_pinmux(0xE, 5, EMC_IO, FUNC3); // PE_5: D24
scu_pinmux(0xE, 6, EMC_IO, FUNC3); // PE_6: D25
scu_pinmux(0xE, 7, EMC_IO, FUNC3); // PE_7: D26
scu_pinmux(0xE, 8, EMC_IO, FUNC3); // PE_8: D27
scu_pinmux(0xE, 9, EMC_IO, FUNC3); // PE_9: D28
scu_pinmux(0xE, 10, EMC_IO, FUNC3); // PE_10: D29
scu_pinmux(0xE, 11, EMC_IO, FUNC3); // PE_11: D30
scu_pinmux(0xE, 12, EMC_IO, FUNC3); // PE_12: D31
// Address line configuration
scu_pinmux(0x2, 9, EMC_IO, FUNC3); // P2_9: A0
scu_pinmux(0x2, 10, EMC_IO, FUNC3); // P2_10: A1
scu_pinmux(0x2, 11, EMC_IO, FUNC3); // P2_11: A2
scu_pinmux(0x2, 12, EMC_IO, FUNC3); // P2_12: A3
scu_pinmux(0x2, 13, EMC_IO, FUNC3); // P2_13: A4
scu_pinmux(0x1, 0, EMC_IO, FUNC2); // P1_0: A5
scu_pinmux(0x1, 1, EMC_IO, FUNC2); // P1_1: A6
scu_pinmux(0x1, 2, EMC_IO, FUNC2); // P1_2: A7
scu_pinmux(0x2, 8, EMC_IO, FUNC3); // P2_8: A8
scu_pinmux(0x2, 7, EMC_IO, FUNC3); // P2_7: A9
scu_pinmux(0x2, 6, EMC_IO, FUNC2); // P2_6: A10
scu_pinmux(0x2, 2, EMC_IO, FUNC2); // P2_2: A11
scu_pinmux(0x2, 1, EMC_IO, FUNC2); // P2_0: A12
scu_pinmux(0x2, 0, EMC_IO, FUNC2); // P2_0: A13
scu_pinmux(0x6, 8, EMC_IO, FUNC1); // P6_8: A14
scu_pinmux(0x6, 7, EMC_IO, FUNC1); // P6_7: A15
scu_pinmux(0xD, 16, EMC_IO, FUNC2); // PD_16: A16
scu_pinmux(0xD, 15, EMC_IO, FUNC2); // PD_15: A17
scu_pinmux(0xE, 0, EMC_IO, FUNC3); // PE_0: A18
scu_pinmux(0xE, 1, EMC_IO, FUNC3); // PE_1: A19
scu_pinmux(0xE, 2, EMC_IO, FUNC3); // PE_2: A20
scu_pinmux(0xE, 3, EMC_IO, FUNC3); // PE_3: A21
scu_pinmux(0xE, 4, EMC_IO, FUNC3); // PE_4: A22
// Control signals for static memory
scu_pinmux(0x1, 6, EMC_IO, FUNC3); // P1_6: WE
scu_pinmux(0x1, 5, EMC_IO, FUNC3); // P1_5: CS0
scu_pinmux(0x1, 3, EMC_IO, FUNC3); // P1_6: OE
scu_pinmux(0x1, 4, EMC_IO, FUNC3); // P1_5: BLS0
scu_pinmux(0x6, 6, EMC_IO, FUNC1); // P1_6: BLS1
scu_pinmux(0xD, 12, EMC_IO, FUNC2); // PD_12: CS2
#if (USE_EXT_DYNAMIC_MEM == YES)
// Control signals for dynamic memory
scu_pinmux(0x6, 9, EMC_IO, FUNC3); // P6_9: DYCS0
scu_pinmux(0x6, 4, EMC_IO, FUNC3); // P6_4: CAS
scu_pinmux(0x6, 5, EMC_IO, FUNC3); // P6_5: RAS
scu_pinmux(0x6, 11, EMC_IO, FUNC3); // P6_11: CKEOUT0
scu_pinmux(0x6, 12, EMC_IO, FUNC3); // P6_12: DQMOUT0
scu_pinmux(0x6, 10, EMC_IO, FUNC3); // P6_10: DQMOUT1
LPC_SCU_CLK(0) = 0 + EMC_IO; // EMC_CLK0 signal on pin CLK0 (needed for SDRAM)
LPC_SCU_CLK(1) = 0 + EMC_IO;
LPC_SCU_CLK(2) = 0 + EMC_IO;
LPC_SCU_CLK(3) = 0 + EMC_IO;
#endif
}
