void Uart0::isr() { uint32_t Status; char data; Uart0 *object; // Process UARTA0 if (g_uart0_object != NULL) { Status = MAP_UARTIntStatus(UARTA0_BASE, true); MAP_UARTIntClear(UARTA0_BASE, Status); object = g_uart0_object; if (Status & UART_INT_RX) { data = MAP_UARTCharGet(UARTA0_BASE); if (object->echo) MAP_UARTCharPut(UARTA0_BASE, data); object->in_buffer()->push_front_isr(data); } if (!object->out_buffer()->is_empty()) { data = object->out_buffer()->pop_isr(); MAP_UARTCharPut(UARTA0_BASE, data); } } }
static void cc32xx_int_handler(struct mgos_uart_state *us) { if (us == NULL) return; struct cc32xx_uart_state *ds = (struct cc32xx_uart_state *) us->dev_data; uint32_t int_st = MAP_UARTIntStatus(ds->base, true /* masked */); us->stats.ints++; uint32_t int_dis = UART_TX_INTS; if (int_st & UART_INT_OE) { us->stats.rx_overflows++; HWREG(ds->base + UART_O_ECR) = 0xff; } if (int_st & (UART_RX_INTS | UART_TX_INTS)) { if (int_st & UART_RX_INTS) { us->stats.rx_ints++; struct cs_rbuf *irxb = &ds->isr_rx_buf; cc32xx_uart_rx_bytes(ds->base, irxb); if (us->cfg.rx_fc_type == MGOS_UART_FC_SW && irxb->used >= CC32xx_UART_ISR_RX_BUF_FC_THRESH && !us->xoff_sent) { MAP_UARTCharPut(ds->base, MGOS_UART_XOFF_CHAR); us->xoff_sent = true; } /* Do not disable RX ints if we have space in the ISR buffer. */ if (irxb->avail == 0) int_dis |= UART_RX_INTS; } if (int_st & UART_TX_INTS) us->stats.tx_ints++; mgos_uart_schedule_dispatcher(us->uart_no, true /* from_isr */); } MAP_UARTIntDisable(ds->base, int_dis); MAP_UARTIntClear(ds->base, int_st); }
//-------------------------------- extern "C" void esp8266_UARTIntHandler(void) { uint32_t ui32Ints = MAP_UARTIntStatus(UART_BASE, true); MAP_UARTIntClear(UART_BASE, ui32Ints); if (pTheOneAndOnlyEsp8266) { pTheOneAndOnlyEsp8266->OnUart(ui32Ints); } }
STATIC void UARTGenericIntHandler(uint32_t uart_id) { pyb_uart_obj_t *self; uint32_t status; if ((self = pyb_uart_find(uart_id))) { status = MAP_UARTIntStatus(self->reg, true); // receive interrupt if (status & (UART_INT_RX | UART_INT_RT)) { MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT); while (UARTCharsAvail(self->reg)) { int data = MAP_UARTCharGetNonBlocking(self->reg); if (MICROPY_STDIO_UART == self->uart_id && data == user_interrupt_char) { // raise exception when interrupts are finished mpexception_keyboard_nlr_jump(); } else if (self->read_buf_len != 0) { uint16_t next_head = (self->read_buf_head + 1) % self->read_buf_len; if (next_head != self->read_buf_tail) { // only store data if room in buf self->read_buf[self->read_buf_head] = data; self->read_buf_head = next_head; } } } } } }
/// \method deinit() /// Turn off the UART bus. STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) { pyb_uart_obj_t *self = self_in; uint uartPerh; switch (self->uart_id) { case PYB_UART_0: uartPerh = PRCM_UARTA0; break; case PYB_UART_1: uartPerh = PRCM_UARTA1; break; default: return mp_const_none; } self->enabled = false; MAP_UARTIntDisable(self->reg, UART_INT_RX | UART_INT_RT); MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT); MAP_UARTIntUnregister(self->reg); MAP_UARTDisable(self->reg); MAP_PRCMPeripheralClkDisable(uartPerh, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); return mp_const_none; }
//***************************************************************************** // //! Interrupt handler for UART interupt //! //! \param None //! //! \return None //! //***************************************************************************** static void UARTIntHandler() { // // Check if RX // if(!bRxDone) { // // Disable UART RX DMA // MAP_UARTDMADisable(UARTA0_BASE,UART_DMA_RX); // // Siganl RX done // bRxDone = true; } else { // // Disable UART TX DMA // MAP_UARTDMADisable(UARTA0_BASE,UART_DMA_TX); } // // Clear the UART Interrupt // MAP_UARTIntClear(UARTA0_BASE,UART_INT_DMATX|UART_INT_DMARX); }
static int int_uart_rx_get_flag( elua_int_resnum resnum, int clear ) { int flag = ( MAP_UARTIntStatus( uart_base[ resnum ], false ) & uart_int_mask ) == uart_int_mask ? 1 : 0; if( clear ) MAP_UARTIntClear( uart_base[ resnum ], uart_int_mask ); return flag; }
void mgos_uart_hal_dispatch_tx_top(struct mgos_uart_state *us) { struct cc32xx_uart_state *ds = (struct cc32xx_uart_state *) us->dev_data; struct mbuf *txb = &us->tx_buf; size_t len = 0; while (len < txb->len && MAP_UARTSpaceAvail(ds->base)) { HWREG(ds->base + UART_O_DR) = *(txb->buf + len); len++; } mbuf_remove(txb, len); us->stats.tx_bytes += len; MAP_UARTIntClear(ds->base, UART_TX_INTS); }
void rt_hw_uart_isr(struct rt_lm3s_serial* serial) { rt_device_t device; rt_uint32_t status; device = (struct rt_device*)serial; status = MAP_UARTIntStatus(serial->hw_base, true); /* clear interrupt status */ MAP_UARTIntClear(serial->hw_base, status); if (device->flag & RT_DEVICE_FLAG_INT_RX) { char ch; rt_base_t level; while (MAP_UARTCharsAvail(serial->hw_base)) { ch = MAP_UARTCharGetNonBlocking(serial->hw_base); /* disable interrupt */ level = rt_hw_interrupt_disable(); /* read character */ serial->rx_buffer[serial->save_index] = ch; serial->save_index ++; if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) serial->save_index = 0; /* if the next position is read index, discard this 'read char' */ if (serial->save_index == serial->read_index) { serial->read_index ++; if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) serial->read_index = 0; } /* enable interrupt */ rt_hw_interrupt_enable(level); } /* invoke callback */ if(device->rx_indicate != RT_NULL) { rt_int32_t length; length = serial->save_index - serial->read_index; if (length < 0) length += RT_UART_RX_BUFFER_SIZE; device->rx_indicate(device, length); } } }
void UARTIntHandler() { u32 temp; int c; temp = MAP_UARTIntStatus(uart_base[ CON_UART_ID ], true); MAP_UARTIntClear(uart_base[ CON_UART_ID ], temp); while( MAP_UARTCharsAvail( uart_base[ CON_UART_ID ] ) ) { c = MAP_UARTCharGetNonBlocking( uart_base[ CON_UART_ID ] ); buf_write( BUF_ID_UART, CON_UART_ID, ( t_buf_data* )&c ); } }
static void UARTIntHandler() { if(!bRxDone) { MAP_UARTDMADisable(UARTA0_BASE,UART_DMA_RX); bRxDone = true; } else { MAP_UARTDMADisable(UARTA0_BASE,UART_DMA_TX); } MAP_UARTIntClear(UARTA0_BASE,UART_INT_DMATX|UART_INT_DMARX); }
void Uart4IntHandler(void) { UartChannelData* const pChannelData = uart2UartChannelData[UART_4]; const uint32_t status = MAP_UARTIntStatus(pChannelData->base, true); MAP_UARTIntClear(pChannelData->base, status); if (status & (UART_INT_RX | UART_INT_RT)) { uartReadIntHandler(pChannelData); } if (status & UART_INT_TX) { uartWriteIntHandler(pChannelData); } }
void UART1IntInit(){ //configure Uart MAP_UARTConfigSetExpClk(UARTA1_BASE, MAP_PRCMPeripheralClockGet(PRCM_UARTA1), UART_BAUD_RATE, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); UARTEnable(UARTA1_BASE); // Disable FIFO so RX interrupt triggers on any character MAP_UARTFIFODisable(UARTA1_BASE); // Set interrupt handlers MAP_UARTIntRegister(UARTA1_BASE,receiveMessage); // Clear any interrupts that may have been present MAP_UARTIntClear(UARTA1_BASE, UART_INT_RX); // Enable interrupt MAP_UARTIntEnable(UARTA1_BASE, UART_INT_RX|UART_INT_RT); UARTFIFOEnable(UARTA1_BASE); }
//***************************************************************************** // // The interrupt handler for UART1. This interrupt will occur when a DMA // transfer is complete using the UART1 uDMA channel. It will also be // triggered if the peripheral signals an error. This interrupt handler // will set a flag when each scatter-gather transfer is complete (one for each // of UART RX and TX). // //***************************************************************************** void UART1IntHandler(void) { unsigned long ulStatus; // // Read the interrupt status of the UART. // ulStatus = MAP_UARTIntStatus(UART1_BASE, 1); // // Clear any pending status, even though there should be none since no UART // interrupts were enabled. If UART error interrupts were enabled, then // those interrupts could occur here and should be handled. Since uDMA is // used for both the RX and TX, then neither of those interrupts should be // enabled. // MAP_UARTIntClear(UART1_BASE, ulStatus); // // Count the number of times this interrupt occurred. // g_ulDMAIntCount++; // // Check the UART TX DMA channel to see if it is enabled. When it is // finished with the transfer it will be automatically disabled. // if(!MAP_uDMAChannelIsEnabled(UDMA_CHANNEL_UART1TX)) { g_bTXdone= 1; } // // Check the UART RX DMA channel to see if it is enabled. When it is // finished with the transfer it will be automatically disabled. // if(!MAP_uDMAChannelIsEnabled(UDMA_CHANNEL_UART1RX)) { g_bRXdone= 1; } }
void HardwareSerial::UARTIntHandler(void) { unsigned long ulInts; long lChar; /* Get and clear the current interrupt source(s) */ ulInts = MAP_UARTIntStatus(UART_BASE, true); MAP_UARTIntClear(UART_BASE, ulInts); /* Are we being interrupted because the TX FIFO has space available? */ if(ulInts & UART_INT_TX) { /* Move as many bytes as we can into the transmit FIFO. */ primeTransmit(UART_BASE); /* If the output buffer is empty, turn off the transmit interrupt. */ if(TX_BUFFER_EMPTY) { MAP_UARTIntDisable(UART_BASE, UART_INT_TX); } } if(ulInts & (UART_INT_RT | UART_INT_TX)) { while(MAP_UARTCharsAvail(UART_BASE)) { /* Read a character */ lChar = MAP_UARTCharGetNonBlocking(UART_BASE); /* If there is space in the receive buffer, put the character * there, otherwise throw it away. */ uint8_t volatile full = RX_BUFFER_FULL; if(full) break; rxBuffer[rxWriteIndex] = (unsigned char)(lChar & 0xFF); rxWriteIndex = ((rxWriteIndex) + 1) % rxBufferSize; /* If we wrote anything to the transmit buffer, make sure it actually * gets transmitted. */ } primeTransmit(UART_BASE); MAP_UARTIntEnable(UART_BASE, UART_INT_TX); } }
void mgos_uart_hal_dispatch_rx_top(struct mgos_uart_state *us) { bool recd; struct cc32xx_uart_state *ds = (struct cc32xx_uart_state *) us->dev_data; cs_rbuf_t *irxb = &ds->isr_rx_buf; MAP_UARTIntDisable(ds->base, UART_RX_INTS); recv_more: recd = false; cc32xx_uart_rx_bytes(ds->base, irxb); while (irxb->used > 0 && mgos_uart_rxb_free(us) > 0) { int num_recd = 0; do { uint8_t *data; int num_to_get = MIN(mgos_uart_rxb_free(us), irxb->used); num_recd = cs_rbuf_get(irxb, num_to_get, &data); mbuf_append(&us->rx_buf, data, num_recd); cs_rbuf_consume(irxb, num_recd); us->stats.rx_bytes += num_recd; if (num_recd > 0) recd = true; cc32xx_uart_rx_bytes(ds->base, irxb); } while (num_recd > 0); } /* If we received something during this cycle and there is buffer space * available, "linger" for some more, maybe there's more to come. */ if (recd && mgos_uart_rxb_free(us) > 0 && us->cfg.rx_linger_micros > 0) { /* Magic constants below are tweaked so that the loop takes at most the * configured number of microseconds. */ int ctr = us->cfg.rx_linger_micros * 31 / 12; // HWREG(GPIOA1_BASE + GPIO_O_GPIO_DATA + 8) = 0xFF; /* Pin 64 */ while (ctr-- > 0) { if (MAP_UARTCharsAvail(ds->base)) { us->stats.rx_linger_conts++; goto recv_more; } } // HWREG(GPIOA1_BASE + GPIO_O_GPIO_DATA + 8) = 0; /* Pin 64 */ } MAP_UARTIntClear(ds->base, UART_RX_INTS); }
static void uart_common_rx_handler( int resnum ) { MAP_UARTIntClear( uart_base[ resnum ], uart_int_mask ); while( MAP_UARTCharsAvail( uart_base[ resnum ] ) ) cmn_int_handler( INT_UART_RX, resnum ); }
//------------------------------------------------------------------------------ //new void uart0_int_handler() { unsigned long const ist = MAP_UARTIntStatus(UART_BASE, TRUE); if (ist & (UART_INT_RX | UART_INT_RT)) { MAP_UARTIntClear(UART_BASE, UART_INT_RX|UART_INT_RT); long b; while(MAP_UARTCharsAvail(UART_BASE)) { b = MAP_UARTCharGetNonBlocking(UART_BASE); if (b == -1 || (char)b == '$' || g_rx_buf_len >= UART_BUF_SZ) { g_rx_buf_len = 0; g_rx_buf[g_rx_buf_len++] = b; }else { if (b == 0x0D && g_rx_buf[0] == '$' && g_rx_buf[g_rx_buf_len-3] == '*') // +ёыш ъюэхЎ яръхЄр { if ( g_rx_buf_len > 10) { unsigned char crc; if (g_rx_buf[--g_rx_buf_len] > '9') crc = 0x0A + g_rx_buf[g_rx_buf_len]-'A'; else crc = (g_rx_buf[g_rx_buf_len]-'0'); if (g_rx_buf[--g_rx_buf_len] > '9') crc |= (0x0A + g_rx_buf[g_rx_buf_len]-'A')<< 4; else crc |= (g_rx_buf[g_rx_buf_len]-'0')<< 4; g_rx_buf_len-=2; do{ crc ^= g_rx_buf[g_rx_buf_len]; }while( --g_rx_buf_len ); if (!crc) // CRC { health_count = 0; gps_info.pack_found++; /* Parse packet */ if( !strncmp((char*)g_rx_buf, "$GPGGA", 6) ) { ProcessGPGGA(&g_rx_buf[7]); st[1] =hw_time(); } else if( !strncmp((char*)g_rx_buf, "$GPRMC", 6)) { ProcessGPRMC(&g_rx_buf[7]); // gps_pps_counter=0; // // st[0] =hw_time(); } }else { gps_info.crc_error++; } } g_rx_buf_len = 0; }else if (b != 0x0A) g_rx_buf[g_rx_buf_len++] = b; } }//while } ///// if (ist & UART_INT_TX) { MAP_UARTIntClear(UART_BASE, UART_INT_TX); tx_pkt_snd_one(); } }
Uart0::Error Uart0::config_uart() { if (is_open()) return kPortAlreadyOpen; uint32_t data_bits_cc3200; switch (data_bits) { case 5: data_bits_cc3200 = UART_CONFIG_WLEN_5; break; case 6: data_bits_cc3200 = UART_CONFIG_WLEN_6; break; case 7: data_bits_cc3200 = UART_CONFIG_WLEN_7; break; case 8: data_bits_cc3200 = UART_CONFIG_WLEN_8; break; default: return kUnsuportedFeature; } uint32_t stop_bits_cc3200; switch (stop_bits) { case 1: stop_bits_cc3200 = UART_CONFIG_STOP_ONE; break; case 2: stop_bits_cc3200 = UART_CONFIG_STOP_TWO; break; default: return kUnsuportedFeature; } uint32_t parity_cc3200; switch (parity) { case kParityEven: parity_cc3200 = UART_CONFIG_PAR_EVEN; break; case kParityMark: parity_cc3200 = UART_CONFIG_PAR_ONE; break; case kParityNone: parity_cc3200 = UART_CONFIG_PAR_NONE; break; case kParityOdd: parity_cc3200 = UART_CONFIG_PAR_ODD; break; case kParitySpace: parity_cc3200 = UART_CONFIG_PAR_ZERO; break; default: return kUnsuportedFeature; } MAP_UARTConfigSetExpClk(UARTA0_BASE, 80000000, baud, (data_bits_cc3200 | stop_bits_cc3200 | parity_cc3200)); /* * Disable UART to modify the configuration. * This is needed because the SetExpClk function enables the UART */ MAP_UARTDisable(UARTA0_BASE); switch (flow_control) { case kFlowControlNone: MAP_UARTFlowControlSet(UARTA0_BASE, UART_FLOWCONTROL_NONE); break; case kFlowControlHardware: /* Enable RTS/CTS Flow Control */ if (mode == kModeDuplex) MAP_UARTFlowControlSet(UARTA0_BASE, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); if (mode == kModeRxOnly) MAP_UARTFlowControlSet(UARTA0_BASE, UART_FLOWCONTROL_RX); if (mode == kModeTxOnly) MAP_UARTFlowControlSet(UARTA0_BASE, UART_FLOWCONTROL_TX); break; default: return kUnsuportedFeature; break; } /* Register Interrupt */ MAP_UARTIntRegister(UARTA0_BASE, isr); /* Enable Interrupt */ MAP_UARTTxIntModeSet(UARTA0_BASE, UART_TXINT_MODE_EOT); MAP_UARTIntClear(UARTA0_BASE, UART_INT_TX | UART_INT_RX); uint32_t interrupts = 0; if ((mode == kModeDuplex) || (mode == kModeTxOnly)) interrupts |= UART_INT_TX; if ((mode == kModeDuplex) || (mode == kModeRxOnly)) interrupts |= UART_INT_RX; MAP_UARTIntEnable(UARTA0_BASE, interrupts); /* Enable UART */ MAP_UARTEnable(UARTA0_BASE); /* Disable Fifo */ MAP_UARTFIFODisable(UARTA0_BASE); return kOK; }
static void uart_int() { int c = UARTCharGet(CONSOLE_UART); struct prompt_event pe = {.type = PROMPT_CHAR_EVENT, .data = (void *) c}; osi_MsgQWrite(&s_v7_q, &pe, OSI_NO_WAIT); MAP_UARTIntClear(CONSOLE_UART, UART_INT_RX); } void sj_prompt_init_hal(struct v7 *v7) { (void) v7; } static void v7_task(void *arg) { struct v7 *v7 = s_v7; printf("\n\nSmart.JS for CC3200\n"); osi_MsgQCreate(&s_v7_q, "V7", sizeof(struct prompt_event), 32 /* len */); osi_InterruptRegister(CONSOLE_UART_INT, uart_int, INT_PRIORITY_LVL_1); MAP_UARTIntEnable(CONSOLE_UART, UART_INT_RX); sl_Start(NULL, NULL, NULL); v7 = s_v7 = init_v7(&v7); sj_init_timers(v7); sj_init_v7_ext(v7); init_wifi(v7); if (init_fs(v7) != 0) { fprintf(stderr, "FS initialization failed.\n"); } mongoose_init(); sj_init_http(v7); init_i2cjs(v7); /* Common config infrastructure. Mongoose & v7 must be initialized. */ init_device(v7); v7_val_t res; if (v7_exec_file(v7, "sys_init.js", &res) != V7_OK) { fprintf(stderr, "Error: "); v7_fprint(stderr, v7, res); } sj_prompt_init(v7); while (1) { struct prompt_event pe; mongoose_poll(MONGOOSE_POLL_LENGTH_MS); if (osi_MsgQRead(&s_v7_q, &pe, V7_POLL_LENGTH_MS) != OSI_OK) continue; switch (pe.type) { case PROMPT_CHAR_EVENT: { sj_prompt_process_char((char) ((int) pe.data)); break; } case V7_INVOKE_EVENT: { struct v7_invoke_event_data *ied = (struct v7_invoke_event_data *) pe.data; _sj_invoke_cb(v7, ied->func, ied->this_obj, ied->args); v7_disown(v7, &ied->args); v7_disown(v7, &ied->this_obj); v7_disown(v7, &ied->func); free(ied); break; } } } } /* Int vector table, defined in startup_gcc.c */ extern void (*const g_pfnVectors[])(void); void device_reboot(void) { sj_system_restart(); } int main() { MAP_IntVTableBaseSet((unsigned long) &g_pfnVectors[0]); MAP_IntEnable(FAULT_SYSTICK); MAP_IntMasterEnable(); PRCMCC3200MCUInit(); cc3200_leds_init(); /* Console UART init. */ MAP_PRCMPeripheralClkEnable(CONSOLE_UART_PERIPH, PRCM_RUN_MODE_CLK); MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* PIN_55 -> UART0_TX */ MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* PIN_57 -> UART0_RX */ MAP_UARTConfigSetExpClk( CONSOLE_UART, MAP_PRCMPeripheralClockGet(CONSOLE_UART_PERIPH), CONSOLE_BAUD_RATE, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); MAP_UARTFIFODisable(CONSOLE_UART); setvbuf(stdout, NULL, _IONBF, 0); setvbuf(stderr, NULL, _IONBF, 0); VStartSimpleLinkSpawnTask(8); osi_TaskCreate(v7_task, (const signed char *) "v7", V7_STACK_SIZE + 256, NULL, 3, NULL); osi_TaskCreate(blinkenlights_task, (const signed char *) "blink", 256, NULL, 9, NULL); osi_start(); return 0; }
static void uart_int() { struct sj_event e = {.type = PROMPT_CHAR_EVENT, .data = NULL}; MAP_UARTIntClear(CONSOLE_UART, UART_INT_RX | UART_INT_RT); MAP_UARTIntDisable(CONSOLE_UART, UART_INT_RX | UART_INT_RT); osi_MsgQWrite(&s_main_queue, &e, OSI_NO_WAIT); }
static void uart_int() { int c = UARTCharGet(CONSOLE_UART); struct prompt_event pe = {.type = PROMPT_CHAR_EVENT, .data = (void *) c}; osi_MsgQWrite(&s_v7_q, &pe, OSI_NO_WAIT); MAP_UARTIntClear(CONSOLE_UART, UART_INT_RX); } void sj_prompt_init_hal(struct v7 *v7) { (void) v7; } static void v7_task(void *arg) { struct v7 *v7 = s_v7; printf("\n\nSmart.JS for CC3200\n"); osi_MsgQCreate(&s_v7_q, "V7", sizeof(struct prompt_event), 32 /* len */); osi_InterruptRegister(CONSOLE_UART_INT, uart_int, INT_PRIORITY_LVL_1); MAP_UARTIntEnable(CONSOLE_UART, UART_INT_RX); sl_Start(NULL, NULL, NULL); v7 = s_v7 = init_v7(&v7); sj_timers_api_setup(v7); sj_v7_ext_api_setup(v7); sj_init_sys(v7); init_wifi(v7); if (init_fs(v7) != 0) { fprintf(stderr, "FS initialization failed.\n"); } mongoose_init(); sj_http_api_setup(v7); sj_i2c_api_setup(v7); /* Common config infrastructure. Mongoose & v7 must be initialized. */ init_device(v7); v7_val_t res; if (v7_exec_file(v7, "sys_init.js", &res) != V7_OK) { fprintf(stderr, "Error: "); v7_fprint(stderr, v7, res); } sj_prompt_init(v7); while (1) { struct prompt_event pe; mongoose_poll(MONGOOSE_POLL_LENGTH_MS); if (osi_MsgQRead(&s_v7_q, &pe, V7_POLL_LENGTH_MS) != OSI_OK) continue; switch (pe.type) { case PROMPT_CHAR_EVENT: { sj_prompt_process_char((char) ((int) pe.data)); break; } case V7_INVOKE_EVENT: { struct v7_invoke_event_data *ied = (struct v7_invoke_event_data *) pe.data; _sj_invoke_cb(v7, ied->func, ied->this_obj, ied->args); v7_disown(v7, &ied->args); v7_disown(v7, &ied->this_obj); v7_disown(v7, &ied->func); free(ied); break; } } } } /* Int vector table, defined in startup_gcc.c */ extern void (*const g_pfnVectors[])(void); void device_reboot(void) { sj_system_restart(0); }
//***************************************************************************** //! //! The interrupt handler for UART0. This interrupt will occur when a DMA //! transfer is complete using the UART0 uDMA channel.This interrupt handler will //! switch between receive ping-pong buffers A and B. It will also restart a TX //! uDMA transfer if the prior transfer is complete. This will keep the UART //! running continuously (looping TX data back to RX). //! //! \param None //! //! \return None //***************************************************************************** void UART0IntHandler(void) { unsigned long ulStatus; unsigned long ulMode; // // Read the interrupt status of the UART. // ulStatus = MAP_UARTIntStatus(UARTA0_BASE, 1); // // Clear any pending status, even though there should be none since no UART // interrupts were enabled. // MAP_UARTIntClear(UARTA0_BASE, ulStatus); if(uiCount<6) { // // Check the DMA control table to see if the ping-pong "A" transfer is // complete. The "A" transfer uses receive buffer "A", and the primary // control structure. // ulMode = MAP_uDMAChannelModeGet(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT); // // If the primary control structure indicates stop, that means the "A" // receive buffer is done. The uDMA controller should still be receiving // data into the "B" buffer. // if(ulMode == UDMA_MODE_STOP) { // // Increment a counter to indicate data was received into buffer A. // g_ulRxBufACount++; // // Set up the next transfer for the "A" buffer, using the primary // control structure. When the ongoing receive into the "B" buffer is // done, the uDMA controller will switch back to this one. // UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, sizeof(g_ucRxBufA),UDMA_SIZE_8, UDMA_ARB_4, (void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE, g_ucRxBufA, UDMA_DST_INC_8); } // // Check the DMA control table to see if the ping-pong "B" transfer is // complete. The "B" transfer uses receive buffer "B", and the alternate // control structure. // ulMode = MAP_uDMAChannelModeGet(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT); // // If the alternate control structure indicates stop, that means the "B" // receive buffer is done. The uDMA controller should still be receiving // data into the "A" buffer. // if(ulMode == UDMA_MODE_STOP) { // // Increment a counter to indicate data was received into buffer A. // g_ulRxBufBCount++; // // Set up the next transfer for the "B" buffer, using the alternate // control structure. When the ongoing receive into the "A" buffer is // done, the uDMA controller will switch back to this one. // UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, sizeof(g_ucRxBufB),UDMA_SIZE_8, UDMA_ARB_4,(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE, g_ucRxBufB, UDMA_DST_INC_8); } // // If the UART0 DMA TX channel is disabled, that means the TX DMA transfer // is done. // if(!MAP_uDMAChannelIsEnabled(UDMA_CH9_UARTA0_TX)) { g_ulTxCount++; // // Start another DMA transfer to UART0 TX. // UDMASetupTransfer(UDMA_CH9_UARTA0_TX| UDMA_PRI_SELECT, UDMA_MODE_BASIC, sizeof(g_ucTxBuf),UDMA_SIZE_8, UDMA_ARB_4,g_ucTxBuf, UDMA_SRC_INC_8, (void *)(UARTA0_BASE + UART_O_DR), UDMA_DST_INC_NONE); // // The uDMA TX channel must be re-enabled. // MAP_uDMAChannelEnable(UDMA_CH9_UARTA0_TX); } } else { UARTDone=1; MAP_UARTIntUnregister(UARTA0_BASE); } }