static void matrix_configure_slave_h32mx(void)
{
unsigned int ssr_setting;
unsigned int sasplit_setting;
unsigned int srtop_setting;
/* 0: Bridge from H32MX to H64MX: Not Secured */
/* 1: H32MX Peripheral Bridge 0: Not Secured */
/* 2: H32MX Peripheral Bridge 1: Not Secured */
/*
* 3: External Bus Interface
* EBI CS0 Memory(256M) ----> Slave Region 0, 1
* EBI CS1 Memory(256M) ----> Slave Region 2, 3
* EBI CS2 Memory(256M) ----> Slave Region 4, 5
* EBI CS3 Memory(128M) ----> Slave Region 6
* NFC Command Registers(128M) -->Slave Region 7
* NANDFlash(EBI CS3) --> Slave Region 6: Non-Secure
*/
srtop_setting = MATRIX_SRTOP(6, MATRIX_SRTOP_VALUE_128M);
srtop_setting |= MATRIX_SRTOP(7, MATRIX_SRTOP_VALUE_128M);
sasplit_setting = MATRIX_SASPLIT(6, MATRIX_SASPLIT_VALUE_128M);
sasplit_setting |= MATRIX_SASPLIT(7, MATRIX_SASPLIT_VALUE_128M);
ssr_setting = (MATRIX_LANSECH_NS(6)
| MATRIX_RDNSECH_NS(6)
| MATRIX_WRNSECH_NS(6));
ssr_setting |= (MATRIX_LANSECH_NS(7)
| MATRIX_RDNSECH_NS(7)
| MATRIX_WRNSECH_NS(7));
matrix_configure_slave_security(matrix32_base(),
H32MX_EXTERNAL_EBI,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 4: NFC SRAM (4K): Non-Secure */
srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_8K);
sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_8K);
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_RDNSECH_NS(0)
| MATRIX_WRNSECH_NS(0));
matrix_configure_slave_security(matrix32_base(),
H32MX_NFC_SRAM,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 5:
* USB Device High Speed Dual Port RAM (DPR): 1M
* USB Host OHCI registers: 1M
* USB Host EHCI registers: 1M
*/
srtop_setting = (MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_1M)
| MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_1M)
| MATRIX_SRTOP(2, MATRIX_SRTOP_VALUE_1M));
sasplit_setting = (MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_1M)
| MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_1M)
| MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_1M));
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_LANSECH_NS(1)
| MATRIX_LANSECH_NS(2)
| MATRIX_RDNSECH_NS(0)
| MATRIX_RDNSECH_NS(1)
| MATRIX_RDNSECH_NS(2)
| MATRIX_WRNSECH_NS(0)
| MATRIX_WRNSECH_NS(1)
| MATRIX_WRNSECH_NS(2));
matrix_configure_slave_security(matrix32_base(),
H32MX_USB,
srtop_setting,
sasplit_setting,
ssr_setting);
}
static int matrix_configure_slave(void)
{
unsigned int ddr_port;
unsigned int ssr_setting, sasplit_setting, srtop_setting;
/*
* Matrix 0 (H64MX)
*/
/*
* 0: Bridge from H64MX to AXIMX
* (Internal ROM, Crypto Library, PKCC RAM): Always Secured
*/
/* 1: H64MX Peripheral Bridge */
/* 2: Video Decoder 1M: Non-Secure */
srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_1M);
sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_1M);
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_RDNSECH_NS(0)
| MATRIX_WRNSECH_NS(0));
matrix_configure_slave_security(AT91C_BASE_MATRIX64,
H64MX_SLAVE_VIDEO_DECODER,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 4 ~ 10 DDR2 Port1 ~ 7: Non-Secure */
srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128M);
sasplit_setting = (MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_128M)
| MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_128M)
| MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_128M)
| MATRIX_SASPLIT(3, MATRIX_SASPLIT_VALUE_128M));
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_LANSECH_NS(1)
| MATRIX_LANSECH_NS(2)
| MATRIX_LANSECH_NS(3)
| MATRIX_RDNSECH_NS(0)
| MATRIX_RDNSECH_NS(1)
| MATRIX_RDNSECH_NS(2)
| MATRIX_RDNSECH_NS(3)
| MATRIX_WRNSECH_NS(0)
| MATRIX_WRNSECH_NS(1)
| MATRIX_WRNSECH_NS(2)
| MATRIX_WRNSECH_NS(3));
/* DDR port 0 not used from NWd */
for (ddr_port = 1; ddr_port < 8; ddr_port++) {
matrix_configure_slave_security(AT91C_BASE_MATRIX64,
(H64MX_SLAVE_DDR2_PORT_0 + ddr_port),
srtop_setting,
sasplit_setting,
ssr_setting);
}
/*
* 11: Internal SRAM 128K
* TOP0 is set to 128K
* SPLIT0 is set to 64K
* LANSECH0 is set to 0, the low area of region 0 is the Securable one
* RDNSECH0 is set to 0, region 0 Securable area is secured for reads.
* WRNSECH0 is set to 0, region 0 Securable area is secured for writes
*/
srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128K);
sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_64K);
ssr_setting = (MATRIX_LANSECH_S(0)
| MATRIX_RDNSECH_S(0)
| MATRIX_WRNSECH_S(0));
matrix_configure_slave_security(AT91C_BASE_MATRIX64,
H64MX_SLAVE_INTERNAL_SRAM,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 12: Bridge from H64MX to H32MX */
/*
* Matrix 1 (H32MX)
*/
/* 0: Bridge from H32MX to H64MX: Not Secured */
/* 1: H32MX Peripheral Bridge 0: Not Secured */
/* 2: H32MX Peripheral Bridge 1: Not Secured */
/*
* 3: External Bus Interface
* EBI CS0 Memory(256M) ----> Slave Region 0, 1
* EBI CS1 Memory(256M) ----> Slave Region 2, 3
* EBI CS2 Memory(256M) ----> Slave Region 4, 5
* EBI CS3 Memory(128M) ----> Slave Region 6
* NFC Command Registers(128M) -->Slave Region 7
*
* NANDFlash(EBI CS3) --> Slave Region 6: Non-Secure
*/
srtop_setting = MATRIX_SRTOP(6, MATRIX_SRTOP_VALUE_128M);
srtop_setting |= MATRIX_SRTOP(7, MATRIX_SRTOP_VALUE_128M);
sasplit_setting = MATRIX_SASPLIT(6, MATRIX_SASPLIT_VALUE_128M);
sasplit_setting |= MATRIX_SASPLIT(7, MATRIX_SASPLIT_VALUE_128M);
ssr_setting = (MATRIX_LANSECH_NS(6)
| MATRIX_RDNSECH_NS(6)
| MATRIX_WRNSECH_NS(6));
ssr_setting |= (MATRIX_LANSECH_NS(7)
| MATRIX_RDNSECH_NS(7)
| MATRIX_WRNSECH_NS(7));
matrix_configure_slave_security(AT91C_BASE_MATRIX32,
H32MX_EXTERNAL_EBI,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 4: NFC SRAM (4K): Non-Secure */
srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_8K);
sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_8K);
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_RDNSECH_NS(0)
| MATRIX_WRNSECH_NS(0));
matrix_configure_slave_security(AT91C_BASE_MATRIX32,
H32MX_NFC_SRAM,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 5:
* USB Device High Speed Dual Port RAM (DPR): 1M
* USB Host OHCI registers: 1M
* USB Host EHCI registers: 1M
*/
srtop_setting = (MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_1M)
| MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_1M)
| MATRIX_SRTOP(2, MATRIX_SRTOP_VALUE_1M));
sasplit_setting = (MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_1M)
| MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_1M)
| MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_1M));
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_LANSECH_NS(1)
| MATRIX_LANSECH_NS(2)
| MATRIX_RDNSECH_NS(0)
| MATRIX_RDNSECH_NS(1)
| MATRIX_RDNSECH_NS(2)
| MATRIX_WRNSECH_NS(0)
| MATRIX_WRNSECH_NS(1)
| MATRIX_WRNSECH_NS(2));
matrix_configure_slave_security(AT91C_BASE_MATRIX32,
H32MX_USB,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 6: Soft Modem (1M): Non-Secure */
srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_1M);
sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_1M);
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_RDNSECH_NS(0)
| MATRIX_WRNSECH_NS(0));
matrix_configure_slave_security(AT91C_BASE_MATRIX32,
H32MX_SMD,
srtop_setting,
sasplit_setting,
ssr_setting);
return 0;
}
static void matrix_configure_slave_h64mx(void)
{
unsigned int ddr_port;
unsigned int ssr_setting;
unsigned int sasplit_setting;
unsigned int srtop_setting;
/*
* 0: Bridge from H64MX to AXIMX
* (Internal ROM, Crypto Library, PKCC RAM): Always Secured
*/
/* 1: H64MX Peripheral Bridge: SDMMC0, SDMMC1 Non-Secure */
srtop_setting = MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_128M)
| MATRIX_SRTOP(2, MATRIX_SRTOP_VALUE_128M);
sasplit_setting = MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_128M)
| MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_128M);
ssr_setting = (MATRIX_LANSECH_NS(1)
| MATRIX_LANSECH_NS(2)
| MATRIX_RDNSECH_NS(1)
| MATRIX_RDNSECH_NS(2)
| MATRIX_WRNSECH_NS(1)
| MATRIX_WRNSECH_NS(2));
matrix_configure_slave_security(matrix64_base(),
H64MX_SLAVE_PERI_BRIDGE,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 2 ~ 9 DDR2 Port1 ~ 7: Non-Secure, except op-tee tee/ta memory */
srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128M);
sasplit_setting = (MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_128M)
| MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_128M)
| MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_8M)
| MATRIX_SASPLIT(3, MATRIX_SASPLIT_VALUE_128M));
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_LANSECH_NS(1)
| MATRIX_LANSECH_S(2)
| MATRIX_LANSECH_NS(3)
| MATRIX_RDNSECH_NS(0)
| MATRIX_RDNSECH_NS(1)
| MATRIX_RDNSECH_S(2)
| MATRIX_RDNSECH_NS(3)
| MATRIX_WRNSECH_NS(0)
| MATRIX_WRNSECH_NS(1)
| MATRIX_WRNSECH_S(2)
| MATRIX_WRNSECH_NS(3));
/* DDR port 0 not used from NWd */
for (ddr_port = 1; ddr_port < 8; ddr_port++) {
matrix_configure_slave_security(matrix64_base(),
(H64MX_SLAVE_DDR2_PORT_0 + ddr_port),
srtop_setting,
sasplit_setting,
ssr_setting);
}
/* 10: Internal SRAM 128K: Non-Secure */
srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128K);
sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_128K);
ssr_setting = (MATRIX_LANSECH_NS(0)
| MATRIX_RDNSECH_NS(0)
| MATRIX_WRNSECH_NS(0));
matrix_configure_slave_security(matrix64_base(),
H64MX_SLAVE_INTERNAL_SRAM,
srtop_setting,
sasplit_setting,
ssr_setting);
/* 11: Internal SRAM 128K (Cache L2): Default */
/* 12: QSPI0: Default */
/* 13: QSPI1: Default */
/* 14: AESB: Default */
}