void fbcs_init(void)
{
writeb(0x3E, MCFGPIO_PAR_CS);
/* Latch chip select */
writel(0x10080000, MCF_FBCS1_CSAR);
writel(0x002A3780, MCF_FBCS1_CSCR);
writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
/* Initialize latch to drive signals to inactive states */
writew(0xffff, 0x10080000);
/* External SRAM */
writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
writel(MCF_FBCS_CSCR_PS_16 |
MCF_FBCS_CSCR_AA |
MCF_FBCS_CSCR_SBM |
MCF_FBCS_CSCR_WS(1),
MCF_FBCS1_CSCR);
writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
/* Boot Flash connected to FBCS0 */
writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
writel(MCF_FBCS_CSCR_PS_16 |
MCF_FBCS_CSCR_BEM |
MCF_FBCS_CSCR_AA |
MCF_FBCS_CSCR_SBM |
MCF_FBCS_CSCR_WS(7),
MCF_FBCS0_CSCR);
writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
}
void fbcs_init(void)
{
MCF_GPIO_PAR_CS = 0x0000003E;
/* Latch chip select */
MCF_FBCS1_CSAR = 0x10080000;
MCF_FBCS1_CSCR = 0x002A3780;
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
/* Initialize latch to drive signals to inactive states */
*((u16 *)(0x10080000)) = 0xFFFF;
/* External SRAM */
MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_SBM
| MCF_FBCS_CSCR_WS(1));
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
| MCF_FBCS_CSMR_V);
/* Boot Flash connected to FBCS0 */
MCF_FBCS0_CSAR = FLASH_ADDRESS;
MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
| MCF_FBCS_CSCR_BEM
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_SBM
| MCF_FBCS_CSCR_WS(7));
MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
| MCF_FBCS_CSMR_V);
}
/*********************************************************************
* init_chip_selects - Chip Select Module (FlexBus) *
**********************************************************************/
void init_chip_selects(void)
{
/* Chip Select 1 disabled (CSMR1[V] = 0) */
MCF_FBCS1_CSMR = 0;
/* Chip Select 2 disabled (CSMR2[V] = 0) */
MCF_FBCS2_CSMR = 0;
/* Chip Select 3 disabled (CSMR3[V] = 0) */
MCF_FBCS3_CSMR = 0;
/* Chip Select 4 disabled (CSMR4[V] = 0) */
MCF_FBCS4_CSMR = 0;
/* Chip Select 5 disabled (CSMR5[V] = 0) */
MCF_FBCS5_CSMR = 0;
/* Chip Select 0: 2 MB of Flash at base address $00000000
Port size = 16 bits
Assert chip select on first rising clock edge after address is asserted
Generate internal transfer acknowledge after 7 wait states
Address is held for 1 clock at end of read and write cycles
*/
MCF_FBCS0_CSAR = 0;
MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
(0x1 << 9) | MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_PS(0x2) | MCF_FBCS_CSCR_BEM;
MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) | MCF_FBCS_CSMR_V;
}
static void fbcs_init (void)
{
/* NAND Flash connected to FBCS0 */
MCF_FBCS0_CSAR = FLASH0_ADDRESS;
MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
| MCF_FBCS_CSCR_BEM
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_WS(0x1F));
MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_256M
| MCF_FBCS_CSMR_V);
}
/** Initialize board specific very early inits
*
* @note This code is not allowed to call other code - just init
* your Chipselects and SDRAM stuff here!
*/
void board_init_lowlevel(void)
{
/*
* The phyCORE-MCF548x has a 32MB or 64MB boot flash.
* The is a CF Card and ControlRegs on CS1 and CS2
*/
/* Setup SysGlue Chip-Select for user IOs */
MCF_FBCS_CSAR2 = MCF_FBCS_CSAR_BA(CFG_XPLD_ADDRESS);
MCF_FBCS_CSCR2 = (MCF_FBCS_CSCR_PS_16
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_WS(CFG_XPLD_WAIT_STATES));
MCF_FBCS_CSMR2 = (MCF_FBCS_CSMR_BAM_16M
| MCF_FBCS_CSMR_V);
/* Setup SysGlue Chip-Select for CFCARD */
MCF_FBCS_CSAR1 = MCF_FBCS_CSAR_BA(CFG_CFCARD_ADDRESS);
MCF_FBCS_CSCR1 = (MCF_FBCS_CSCR_PS_16
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_WS(CFG_CFCARD_WAIT_STATES));
MCF_FBCS_CSMR1 = (MCF_FBCS_CSMR_BAM_16M
| MCF_FBCS_CSMR_V);
/* Setup boot flash chip-select */
MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS);
MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32
| MCF_FBCS_CSCR_AA
| MCF_FBCS_CSCR_ASET(1)
| MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES));
MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M
| MCF_FBCS_CSMR_V);
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
{
/*
* Basic configuration and initialization
*/
// 0x000002AA
MCF_SDRAMC_SDRAMDS = (0
| MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
);
// 0x0000001A
MCF_SDRAMC_CS0CFG = (0
| MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS)
| MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE)
);
MCF_SDRAMC_CS1CFG = 0;
MCF_SDRAMC_CS2CFG = 0;
MCF_SDRAMC_CS3CFG = 0;
// 0x73611730
MCF_SDRAMC_SDCFG1 = (0
| MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5))
| MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1))
| MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2))
| MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
| MCF_SDRAMC_SDCFG1_WTLAT(3)
);
// 0x46770000
MCF_SDRAMC_SDCFG2 = (0
| MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2)
| MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR)
| MCF_SDRAMC_SDCFG2_BRD2WT(7)
| MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1)
);
/*
* Precharge and enable write to SDMR
*/
// 0xE10B0002
MCF_SDRAMC_SDCR = (0
| MCF_SDRAMC_SDCR_MODE_EN
| MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_DDR
| MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1
| MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5))
| MCF_SDRAMC_SDCR_IPALL
);
/*
* Write extended mode register
*/
// 0x40010000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LEMR
| MCF_SDRAMC_SDMR_AD(0x0)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Write mode register and reset DLL
*/
// 0x048d0000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LMR
| MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Execute a PALL command
*/
// 0xE10B0002
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
/*
* Perform two REF cycles
*/
// 0xE10B0004
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
/*
* Write mode register and clear reset DLL
*/
// 0x008D0000
MCF_SDRAMC_SDMR = (0
| MCF_SDRAMC_SDMR_BNKAD_LMR
| MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD)
| MCF_SDRAMC_SDMR_CMD
);
/*
* Enable auto refresh and lock SDMR
*/
// 0x610B0000
MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
// 0x710B0F00
MCF_SDRAMC_SDCR |= (0
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_DQS_OE(0xF)
);
}
}
