/* ** This function will activate/deactivate CS line and also enable Tx and Rx ** interrupts of McSPI peripheral. */ static void McSPITransfer(void) { p_tx = txBuffer; p_rx = rxBuffer; /* SPIEN line is forced to low state.*/ McSPICSAssert(SOC_SPI_0_REGS, chNum); /* Enable the Tx/Rx interrupts of McSPI.*/ McSPIIntEnable(SOC_SPI_0_REGS, MCSPI_INT_TX_EMPTY(chNum) | MCSPI_INT_RX_FULL(chNum)); /* Enable the McSPI channel for communication.*/ McSPIChannelEnable(SOC_SPI_0_REGS, chNum); /* Wait until control returns back from McSPI ISR.*/ while(flag); flag = 1; /* Force SPIEN line to the inactive state.*/ McSPICSDeAssert(SOC_SPI_0_REGS, chNum); /* Disable the McSPI channel.*/ McSPIChannelDisable(SOC_SPI_0_REGS, chNum); }
/* ** McSPI Interrupt Service Routine. This function will clear the status of the ** Tx/Rx interrupts when generated. Will write the Tx data on transmit data ** register and also will put the received data from receive data register to ** a location in memory. */ static void McSPIIsr(void) { unsigned int intCode = 0; intCode = McSPIIntStatusGet(SOC_SPI_0_REGS); while(intCode) { if(MCSPI_INT_TX_EMPTY(chNum) == (intCode & MCSPI_INT_TX_EMPTY(chNum))) { McSPIIntStatusClear(SOC_SPI_0_REGS, MCSPI_INT_TX_EMPTY(chNum)); length--; McSPITransmitData(SOC_SPI_0_REGS,(unsigned int)(*p_tx++), chNum); if(!length) { McSPIIntDisable(SOC_SPI_0_REGS, MCSPI_INT_TX_EMPTY(chNum)); McSPIIntStatusClear(SOC_SPI_0_REGS, MCSPI_INT_TX_EMPTY(chNum)); } } if(MCSPI_INT_RX_FULL(chNum) == (intCode & MCSPI_INT_RX_FULL(chNum))) { McSPIIntStatusClear(SOC_SPI_0_REGS, MCSPI_INT_RX_FULL(chNum)); *p_rx++ = (unsigned char) McSPIReceiveData(SOC_SPI_0_REGS, chNum); if(!(length)) { McSPIIntDisable(SOC_SPI_0_REGS, MCSPI_INT_RX_FULL(chNum)); flag = 0; } } intCode = McSPIIntStatusGet(SOC_SPI_0_REGS); } }
/* ** This function will activate/deactivate CS line and also enable Tx and Rx ** interrupts of McSPI peripheral. */ void _mcspi_transfer(Mcspi_t *McspiStruct) { McspiStruct->BuffTmp = McspiStruct->Buff; /* SPIEN line is forced to low state.*/ McSPICSAssert(McspiStruct->BaseAddr, McspiStruct->Channel); /* Enable the Tx/Rx interrupts of McSPI.*/ McSPIIntEnable(McspiStruct->BaseAddr, MCSPI_INT_TX_EMPTY(McspiStruct->Channel) | MCSPI_INT_RX_FULL(McspiStruct->Channel)); /* Enable the McSPI channel for communication.*/ McSPIChannelEnable(McspiStruct->BaseAddr, McspiStruct->Channel); /* Wait until control returns back from McSPI ISR.*/ while(McspiStruct->flag); McspiStruct->flag = 1; /* Force SPIEN line to the inactive state.*/ McSPICSDeAssert(McspiStruct->BaseAddr, McspiStruct->Channel); /* Disable the McSPI channel.*/ McSPIChannelDisable(McspiStruct->BaseAddr, McspiStruct->Channel); }