/* VLPR mode entry routine. Puts the processor into very low power * run mode. In this mode all clocks are enabled, but the core, bus, * and peripheral clocks are limited to 2MHz or less. The flash * clock is limited to 1MHz or less. * * Mode transitions: * RUN -> VLPR * * exit_vlpr() function or an interrupt with LPWUI set can be used * to switch from VLPR back to RUN. The enable_lpwui() and disable_lpwui() * functions can be used to set LPWUI to the desired option prior to * calling enter_vlpr(). * * Parameters: * none */ void enter_vlpr(char lpwui_value) { /* Reduce system clock to < 2MHz */ printf("\n\n\n To communicate in VLPR - Auto-Trim must have been done, then Change Baud Rate to 19200 baud NOW !!!! \n\r"); mcg_pee_2_blpi(); SIM_CLKDIV1 = 0x13330000; //(SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(3) \ // SIM_CLKDIV1_OUTDIV3(3) | SIM_CLKDIV1_OUTDIV4(3)); //core = /2 bus = /4 =flex bus /4 flash clk /4 /* Set the RUNM field to 0b10 for VLPR mode - Need to retain state of LPWUI bit 8 */ /* Set the LPLLSM field to 0b010 for VLPS mode - Need to set state of LPWUI bit 8 */ if(lpwui_value) { MC_PMCTRL = (MC_PMCTRL_LPWUI_MASK // set LPWUI | MC_PMCTRL_RUNM(2)); // set RUNM = 0b10 } else { MC_PMCTRL = (!MC_PMCTRL_LPWUI_MASK // clear LPWUI | MC_PMCTRL_RUNM(2)); // set RUNM = 0b10 } /* Wait for VLPS regulator mode to be confirmed */ while(!(PMC_REGSC & PMC_REGSC_VLPRS_MASK)); // 0 MCU is not in VLPR mode // 1 MCU is in VLPR mode }
/* VLPR mode exit routine. Puts the processor into normal run mode * from VLPR mode. You can transition from VLPR to normal run using * this function or an interrupt with LPWUI set. The enable_lpwui() * and disable_lpwui() functions can be used to set LPWUI to the * desired option prior to calling enter_vlpr(). * * Mode transitions: * VLPR -> RUN * * Parameters: * none */ void exit_vlpr(void) { /* Clear RUNM */ MC_PMCTRL &= ~(MC_PMCTRL_RUNM(0x3)); /* Wait for normal RUN regulation mode to be confirmed */ while (PMC_REGSC & PMC_REGSC_VLPRS_MASK); // 0 MCU is not in VLPR mode // 1 MCU is in VLPR mode while(!(PMC_REGSC & PMC_REGSC_REGONS_MASK)); /* Transition MCG back to the PLL enabled state */ mcg_blpi_2_pee(); //sim_clkdivided back to default SIM_CLKDIV1 = 0x00110000; //(SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(3) \ // SIM_CLKDIV1_OUTDIV3(3) | SIM_CLKDIV1_OUTDIV4(3)); //core = /1 bus = /1 =flex bus /2 flash clk /2 }
boolean _lpm_idle_sleep_check ( void ) { _mqx_uint pmctrl, stop; pmctrl = MC_PMCTRL; stop = SCB_SCR & SCB_SCR_SLEEPDEEP_MASK; /* Idle sleep is available only in normal RUN/WAIT and VLPR/VLPW with LPWUI disabled */ if ((0 == stop) && (0 == (pmctrl & MC_PMCTRL_LPLLSM_MASK)) && (! ((MC_PMCTRL_LPWUI_MASK | MC_PMCTRL_RUNM(2)) == (pmctrl & (MC_PMCTRL_LPWUI_MASK | MC_PMCTRL_RUNM_MASK))))) { return TRUE; } return FALSE; }
MC_PMCTRL_LPWUI_MASK, // Mode PMCTRL register == voltage regulator ON after wakeup 0, // Mode flags == clear settings }, // Kinetis WAIT { MC_PMCTRL_LPWUI_MASK, // Mode PMCTRL register == voltage regulator ON after wakeup LPM_CPU_POWER_MODE_FLAG_USE_WFI, // Mode flags == execute WFI }, // Kinetis STOP { MC_PMCTRL_LPWUI_MASK, // Mode PMCTRL register == voltage regulator ON after wakeup LPM_CPU_POWER_MODE_FLAG_DEEP_SLEEP | LPM_CPU_POWER_MODE_FLAG_USE_WFI, // Mode flags == deepsleep, execute WFI }, // Kinetis VLPR { MC_PMCTRL_RUNM(2), // Mode PMCTRL register == VLPR 0, // Mode flags == clear settings }, // Kinetis VLPW { MC_PMCTRL_RUNM(2), // Mode PMCTRL register == VLPW LPM_CPU_POWER_MODE_FLAG_USE_WFI, // Mode flags == execute WFI }, // Kinetis VLPS { MC_PMCTRL_LPLLSM(2), // Mode PMCTRL register == VLPS LPM_CPU_POWER_MODE_FLAG_DEEP_SLEEP | LPM_CPU_POWER_MODE_FLAG_USE_WFI, // Mode flags == deepsleep, execute WFI }, // Kinetis LLS { MC_PMCTRL_LPWUI_MASK | MC_PMCTRL_LPLLSM(3), // Mode PMCTRL register == voltage regulator ON after wakeup, LLS