// // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, // Byte6Seed, Byte7Seed, ByteEccSeed) // Specifies the write leveling seed for a channel of a socket. // // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, // Byte6Seed, Byte7Seed, ByteEccSeed) // Speicifes the HW RXEN training seed for a channel of a socket // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), PSO_END }; /* * These tables are optional and may be used to adjust memory timing settings */ #include "mm.h" #include "mn.h"
// SEED_A), // WRITE_LEVELING_SEED (ANY_SOCKET, CHANNEL_B, ALL_DIMMS, // 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15), DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, CHANNEL_A, 2), //NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, CHANNEL_B, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MOTHER_BOARD_LAYERS (LAYERS_6), // MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x04, 0x01, 0x02, 0x08, 0x00, 0x00, 0x00, 0x00), // MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff), // MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), #if 0 MEMCLK_DIS_MAP (ANY_SOCKET, ANY_SOCKET, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00, 0x00, 0x00), //MEMCLK_DIS_MAP (ANY_SOCKET, CHANNEL_B, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A, 0x0, 0x0), /* TODO: bit2map, bit3map */ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x04, 0x02, 0x08), CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), #else MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x0F, 0x0F, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00), CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x0f, 0x0f, 0xf, 0xf), /* TODO: bit2map, bit3map */ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x0f, 0x0f, 0x0f, 0xf), CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x0f, 0x0f, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00), #endif PSO_END }; /*
