static void
netx_eth_phy_write(struct net_device *ndev, int phy_id, int reg, int value)
{
unsigned int val;
val = MIIMU_SNRDY | MIIMU_PREAMBLE | MIIMU_PHYADDR(phy_id) |
MIIMU_REGADDR(reg) | MIIMU_PHY_NRES | MIIMU_OPMODE_WRITE |
MIIMU_DATA(value);
writel(val, NETX_MIIMU);
while (readl(NETX_MIIMU) & MIIMU_SNRDY);
}
static int netx_miidev_write(struct mii_device *mdev, int phy_addr,
int reg, int val)
{
debug("%s: addr: 0x%02x reg: 0x%02x val: 0x%04x\n",__func__,
addr, reg, val);
MIIMU_REG = MIIMU_SNRDY | MIIMU_PREAMBLE | MIIMU_PHYADDR(phy_addr) |
MIIMU_REGADDR(reg) | MIIMU_PHY_NRES | MIIMU_OPMODE_WRITE |
MIIMU_DATA(val);
while(MIIMU_REG & MIIMU_SNRDY);
return 0;
}
static int
netx_eth_phy_read(struct net_device *ndev, int phy_id, int reg)
{
unsigned int val;
val = MIIMU_SNRDY | MIIMU_PREAMBLE | MIIMU_PHYADDR(phy_id) |
MIIMU_REGADDR(reg) | MIIMU_PHY_NRES;
writel(val, NETX_MIIMU);
while (readl(NETX_MIIMU) & MIIMU_SNRDY);
return readl(NETX_MIIMU) >> 16;
}
static int netx_miidev_read(struct mii_device *mdev, int phy_addr, int reg)
{
int value;
MIIMU_REG = MIIMU_SNRDY | MIIMU_PREAMBLE | MIIMU_PHYADDR(phy_addr) |
MIIMU_REGADDR(reg) | MIIMU_PHY_NRES;
while(MIIMU_REG & MIIMU_SNRDY);
value = MIIMU_REG >> 16;
debug("%s: addr: 0x%02x reg: 0x%02x val: 0x%04x\n", __func__,
addr, reg, value);
return value;
}