static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, uint32_t mem_value) { SH7750State *s = opaque; switch (MM_REGION_TYPE(addr)) { case MM_ICACHE_ADDR: case MM_ICACHE_DATA: /* do nothing */ break; case MM_ITLB_ADDR: case MM_ITLB_DATA: /* XXXXX */ assert(0); break; case MM_OCACHE_ADDR: case MM_OCACHE_DATA: /* do nothing */ break; case MM_UTLB_ADDR: cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); break; case MM_UTLB_DATA: /* XXXXX */ assert(0); break; default: assert(0); break; } }
static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) { SH7750State *s = opaque; uint32_t ret = 0; switch (MM_REGION_TYPE(addr)) { case MM_ICACHE_ADDR: case MM_ICACHE_DATA: /* do nothing */ break; case MM_ITLB_ADDR: ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr); break; case MM_ITLB_DATA: ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr); break; case MM_OCACHE_ADDR: case MM_OCACHE_DATA: /* do nothing */ break; case MM_UTLB_ADDR: ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr); break; case MM_UTLB_DATA: ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr); break; default: abort(); } return ret; }
static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) { uint32_t ret = 0; switch (MM_REGION_TYPE(addr)) { case MM_ICACHE_ADDR: case MM_ICACHE_DATA: /* do nothing */ break; case MM_ITLB_ADDR: case MM_ITLB_DATA: /* XXXXX */ assert(0); break; case MM_OCACHE_ADDR: case MM_OCACHE_DATA: /* do nothing */ break; case MM_UTLB_ADDR: case MM_UTLB_DATA: /* XXXXX */ assert(0); break; default: assert(0); } return ret; }
static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr, unsigned size) { SH7750State *s = opaque; uint32_t ret = 0; if (size != 4) { return invalid_read(opaque, addr); } switch (MM_REGION_TYPE(addr)) { case MM_ICACHE_ADDR: case MM_ICACHE_DATA: /* do nothing */ break; case MM_ITLB_ADDR: ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); break; case MM_ITLB_DATA: ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); break; case MM_OCACHE_ADDR: case MM_OCACHE_DATA: /* do nothing */ break; case MM_UTLB_ADDR: ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); break; case MM_UTLB_DATA: ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); break; default: abort(); } return ret; }
static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr, uint64_t mem_value, unsigned size) { SH7750State *s = opaque; if (size != 4) { invalid_write(opaque, addr, mem_value); } switch (MM_REGION_TYPE(addr)) { case MM_ICACHE_ADDR: case MM_ICACHE_DATA: /* do nothing */ break; case MM_ITLB_ADDR: cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); break; case MM_ITLB_DATA: cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value); abort(); break; case MM_OCACHE_ADDR: case MM_OCACHE_DATA: /* do nothing */ break; case MM_UTLB_ADDR: cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); break; case MM_UTLB_DATA: cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value); break; default: abort(); break; } }