static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state) { unsigned long mpidr; int cpu, cluster; mpidr = read_mpidr(); cluster = MPIDR_AFFLVL1_VAL(mpidr); cpu = MPIDR_AFFLVL0_VAL(mpidr); /* * Enable CCI coherency for this cluster. * No need for locks as no other cpu is active at the moment. */ if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); /* Zero the jump address in the mailbox for this cpu */ hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); /* Program the GIC per-cpu distributor or re-distributor interface */ gicv2_pcpu_distif_init(); /* Enable the GIC cpu interface */ gicv2_cpuif_enable(); }
static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) { uint32_t cpu, cluster; uint32_t cpuon_id; cpu = MPIDR_AFFLVL0_VAL(mpidr); cluster = MPIDR_AFFLVL1_VAL(mpidr); /* Make sure the cpu is off,Before power up the cpu! */ cpus_id_power_domain(cluster, cpu, pmu_pd_off, CKECK_WFEI_MSK); cpuon_id = (cluster * PLATFORM_CLUSTER0_CORE_COUNT) + cpu; assert(cpuson_flags[cpuon_id] == 0); cpuson_flags[cpuon_id] = PMU_CPU_HOTPLUG; cpuson_entry_point[cpuon_id] = entrypoint; /* Switch boot addr to pmusram */ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); dsb(); cpus_id_power_domain(cluster, cpu, pmu_pd_on, CKECK_WFEI_MSK); mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), (COLD_BOOT_BASE >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); return 0; }
static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr(); sunxi_cpu_off(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr)); while (1) wfi(); }
static int sunxi_pwr_domain_on(u_register_t mpidr) { if (mpidr_is_valid(mpidr) == 0) return PSCI_E_INTERN_FAIL; sunxi_cpu_on(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr)); return PSCI_E_SUCCESS; }
static int hikey_pwr_domain_on(u_register_t mpidr) { int cpu, cluster; int curr_cluster; cluster = MPIDR_AFFLVL1_VAL(mpidr); cpu = MPIDR_AFFLVL0_VAL(mpidr); curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); if (cluster != curr_cluster) hisi_ipc_cluster_on(cpu, cluster); hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); hisi_pwrc_enable_debug(cpu, cluster); hisi_ipc_cpu_on(cpu, cluster); return 0; }
void hikey_pwr_domain_off(const psci_power_state_t *target_state) { unsigned long mpidr; int cpu, cluster; mpidr = read_mpidr(); cluster = MPIDR_AFFLVL1_VAL(mpidr); cpu = MPIDR_AFFLVL0_VAL(mpidr); gicv2_cpuif_disable(); hisi_ipc_cpu_off(cpu, cluster); if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); hisi_ipc_cluster_off(cpu, cluster); } }
static void nonboot_cpus_off(void) { uint32_t boot_cpu, boot_cluster, cpu; boot_cpu = MPIDR_AFFLVL0_VAL(read_mpidr_el1()); boot_cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); /* turn off noboot cpus */ for (cpu = 0; cpu < PLATFORM_CLUSTER0_CORE_COUNT; cpu++) { if (!boot_cluster && (cpu == boot_cpu)) continue; cpus_id_power_domain(0, cpu, pmu_pd_off, CKECK_WFEI_MSK); } for (cpu = 0; cpu < PLATFORM_CLUSTER1_CORE_COUNT; cpu++) { if (boot_cluster && (cpu == boot_cpu)) continue; cpus_id_power_domain(1, cpu, pmu_pd_off, CKECK_WFEI_MSK); } }