static struct hc55516_interface s9s_hc55516Int = { 1, { 100 }};
MACHINE_DRIVER_START(wmssnd_s9s)
MDRV_CPU_ADD(M6808, 1000000)
MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
MDRV_CPU_MEMORY(s9s_readmem, s9s_writemem)
MDRV_INTERLEAVE(50)
MDRV_SOUND_ADD(DAC, s9s_dacInt)
MDRV_SOUND_ADD(HC55516,s9s_hc55516Int)
MDRV_SOUND_ADD(SAMPLES, samples_interface)
MACHINE_DRIVER_END
static MEMORY_READ_START(s11s_readmem)
{ 0x0000, 0x0fff, MRA_RAM},
{ 0x2000, 0x2003, pia_r(S11S_PIA0) },
{ 0x8000, 0xbfff, MRA_BANKNO(S11S_BANK0)}, /* U22 */
{ 0xc000, 0xffff, MRA_BANKNO(S11S_BANK1)}, /* U21 */
MEMORY_END
static MEMORY_WRITE_START(s11s_writemem)
{ 0x0000, 0x0fff, MWA_RAM },
{ 0x1000, 0x1000, s11s_bankSelect},
{ 0x2000, 0x2003, pia_w(S11S_PIA0)},
MEMORY_END
static void s11cs_ym2151IRQ(int state);
static struct DACinterface s11xs_dacInt2 = { 2, { 50,50 }};
static struct hc55516_interface s11b2s_hc55516Int = { 1, { 80 }};
static struct hc55516_interface s11xs_hc55516Int2 = { 2, { 80,80 }};
static struct YM2151interface s11cs_ym2151Int = {
1, 3579545, /* Hz */
{ YM3012_VOL(10,MIXER_PAN_CENTER,30,MIXER_PAN_CENTER) },
if (locals.ramBank == 0x0b) locals.segments[offset].w = (~data & 0x7f) | ((~data & 0x80) << 1) | ((~data & 0x80) << 2);
if (locals.ramBank > 7) logerror("%04x: ram %03x write: %02x\n", activecpu_get_previouspc(), 0x100 * locals.ramBank + offset, data);
// if (locals.ramBank == 0x0a) ppi8255_0_w(offset & 3, data);
}
static WRITE_HANDLER(by8035_port_w) {
if (offset == 2)
{
cpu_setbank(1, memory_region(REGION_CPU1) + 0x1000 + 0x100 * (data & 0x30));
locals.ramBank = data & 0x0f;
}
logerror("%04x: 8035 port %d write = %02x\n", activecpu_get_previouspc(), offset, data);
}
static MEMORY_READ_START(by8035_readmem)
{ 0x0000, 0x0fff, MRA_BANKNO(1) },
{ 0x1000, 0x4fff, MRA_ROM },
{ 0x5000, 0x5fff, MRA_RAM },
MEMORY_END
static MEMORY_WRITE_START(by8035_writemem)
{ 0x0000, 0x0fff, MWA_BANKNO(1) },
{ 0x1000, 0x4fff, MWA_ROM },
{ 0x5000, 0x5fff, MWA_RAM },
MEMORY_END
static PORT_READ_START(by8035_readport)
{ 0x00, 0xff, by8035_ram_r },
{ 0x100, 0x107, by8035_port_r },
MEMORY_END
