int mcequirk_amd_apply(enum mcequirk_amd_flags flags) { uint64_t val; switch ( flags ) { case MCEQUIRK_K8_GART: /* * Enable error reporting for all errors except for GART * TBL walk error reporting, which trips off incorrectly * with AGP GART & 3ware & Cerberus. */ wrmsrl(MSR_IA32_MCx_CTL(4), ~(1ULL << 10)); wrmsrl(MSR_IA32_MCx_STATUS(4), 0ULL); break; case MCEQUIRK_F10_GART: if ( rdmsr_safe(MSR_AMD64_MCx_MASK(4), val) == 0 ) wrmsr_safe(MSR_AMD64_MCx_MASK(4), val | (1 << 10)); break; } return 0; }
enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *ci) { uint32_t i; enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(ci); /* Assume that machine check support is available. * The minimum provided support is at least the K8. */ mce_handler_init(); x86_mce_vector_register(mcheck_cmn_handler); mce_need_clearbank_register(amd_need_clearbank_scan); for ( i = 0; i < nr_mce_banks; i++ ) { if ( quirkflag == MCEQUIRK_K8_GART && i == 4 ) mcequirk_amd_apply(quirkflag); else { /* Enable error reporting of all errors */ wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL); wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL); } } if ( ci->x86 == 0xf ) return mcheck_amd_k8; if ( quirkflag == MCEQUIRK_F10_GART ) mcequirk_amd_apply(quirkflag); x86_mce_callback_register(amd_f10_handler); mce_recoverable_register(mc_amd_recoverable_scan); mce_register_addrcheck(mc_amd_addrcheck); return mcheck_amd_famXX; }
{ TBOX | W64, 3, TXS_MCX_CONTROL, 0 }, /* Uncore */ { TBOX | W64, 4, TXS_MCX_CONTROL, 0 }, /* Uncore */ { TBOX | W64, 5, TXS_MCX_CONTROL, 0 }, /* Uncore */ { TBOX | W64, 6, TXS_MCX_CONTROL, 0 }, /* Uncore */ { TBOX | W64, 7, TXS_MCX_CONTROL, 0 }, /* Uncore */ #endif }; #if RAS_SAVE_MSR static RegRec susp_msr[] = { /* Used in file */ { GMSR, 0, MSR_IA32_MCG_STATUS, 0 }, /* Uncore, kernel */ }; #if RAS_SAVE_CPU_MSR static RegRec susp_lcl_msr[4 * CONFIG_NR_CPUS] = { /* Used in file */ { LMSR, 0, MSR_IA32_MCx_CTL(0), 0 }, /* Core, kernel */ { LMSR, 0, MSR_IA32_MCx_CTL(1), 0 }, /* Core, kernel */ { LMSR, 0, MSR_IA32_MCx_CTL(2), 0 }, /* Core, kernel */ { LMSR, 0, MSR_IA32_MCG_CTL, 0 }, /* kernel */ /* * The remaining entries is setup/replicated by pm_init() */ }; #endif #endif static void one_mmio_rd(RegRec * r) { switch(r->box & 0xf) {