static int mt7603_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue, const struct ieee80211_tx_queue_params *params) { struct mt7603_dev *dev = hw->priv; u16 cw_min = (1 << 5) - 1; u16 cw_max = (1 << 10) - 1; u32 val; queue = dev->mt76.q_tx[queue].hw_idx; if (params->cw_min) cw_min = params->cw_min; if (params->cw_max) cw_max = params->cw_max; mutex_lock(&dev->mutex); mt7603_mac_stop(dev); val = mt76_rr(dev, MT_WMM_TXOP(queue)); val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(queue)); val |= params->txop << MT_WMM_TXOP_SHIFT(queue); mt76_wr(dev, MT_WMM_TXOP(queue), val); val = mt76_rr(dev, MT_WMM_AIFSN); val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(queue)); val |= params->aifs << MT_WMM_AIFSN_SHIFT(queue); mt76_wr(dev, MT_WMM_AIFSN, val); val = mt76_rr(dev, MT_WMM_CWMIN); val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(queue)); val |= cw_min << MT_WMM_CWMIN_SHIFT(queue); mt76_wr(dev, MT_WMM_CWMIN, val); val = mt76_rr(dev, MT_WMM_CWMAX(queue)); val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(queue)); val |= cw_max << MT_WMM_CWMAX_SHIFT(queue); mt76_wr(dev, MT_WMM_CWMAX(queue), val); mt7603_mac_start(dev); mutex_unlock(&dev->mutex); return 0; }
static int mt76x2_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue, const struct ieee80211_tx_queue_params *params) { struct mt76x2_dev *dev = hw->priv; u8 cw_min = 5, cw_max = 10, qid; u32 val; qid = dev->mt76.q_tx[queue].hw_idx; if (params->cw_min) cw_min = fls(params->cw_min); if (params->cw_max) cw_max = fls(params->cw_max); val = FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop) | FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) | FIELD_PREP(MT_EDCA_CFG_CWMIN, cw_min) | FIELD_PREP(MT_EDCA_CFG_CWMAX, cw_max); mt76_wr(dev, MT_EDCA_CFG_AC(qid), val); val = mt76_rr(dev, MT_WMM_TXOP(qid)); val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(qid)); val |= params->txop << MT_WMM_TXOP_SHIFT(qid); mt76_wr(dev, MT_WMM_TXOP(qid), val); val = mt76_rr(dev, MT_WMM_AIFSN); val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(qid)); val |= params->aifs << MT_WMM_AIFSN_SHIFT(qid); mt76_wr(dev, MT_WMM_AIFSN, val); val = mt76_rr(dev, MT_WMM_CWMIN); val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(qid)); val |= cw_min << MT_WMM_CWMIN_SHIFT(qid); mt76_wr(dev, MT_WMM_CWMIN, val); val = mt76_rr(dev, MT_WMM_CWMAX); val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(qid)); val |= cw_max << MT_WMM_CWMAX_SHIFT(qid); mt76_wr(dev, MT_WMM_CWMAX, val); return 0; }
static int mt76_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue, const struct ieee80211_tx_queue_params *params) { struct mt76_dev *dev = hw->priv; u8 cw_min = 5, cw_max = 10; u32 val; if (params->cw_min) cw_min = fls(params->cw_min); if (params->cw_max) cw_max = fls(params->cw_max); val = MT76_SET(MT_EDCA_CFG_TXOP, params->txop) | MT76_SET(MT_EDCA_CFG_AIFSN, params->aifs) | MT76_SET(MT_EDCA_CFG_CWMIN, cw_min) | MT76_SET(MT_EDCA_CFG_CWMAX, cw_max); mt76_wr(dev, MT_EDCA_CFG_AC(queue), val); val = mt76_rr(dev, MT_WMM_TXOP(queue)); val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(queue)); val |= params->txop << MT_WMM_TXOP_SHIFT(queue); mt76_wr(dev, MT_WMM_TXOP(queue), val); val = mt76_rr(dev, MT_WMM_AIFSN); val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(queue)); val |= params->aifs << MT_WMM_AIFSN_SHIFT(queue); mt76_wr(dev, MT_WMM_AIFSN, val); val = mt76_rr(dev, MT_WMM_CWMIN); val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(queue)); val |= cw_min << MT_WMM_CWMIN_SHIFT(queue); mt76_wr(dev, MT_WMM_CWMIN, val); val = mt76_rr(dev, MT_WMM_CWMAX); val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(queue)); val |= cw_max << MT_WMM_CWMAX_SHIFT(queue); mt76_wr(dev, MT_WMM_CWMAX, val); return 0; }