static void __init mv78xx0_pcie_preinit(void)
{
int i;
u32 size_each;
u32 start;
int win = 0;
pcie_io_space.name = "PCIe I/O Space";
pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
pcie_io_space.end =
MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
pcie_io_space.flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource, &pcie_io_space))
panic("can't allocate PCIe I/O space");
if (num_pcie_ports > 7)
panic("invalid number of PCIe ports");
size_each = pcie_port_size[num_pcie_ports];
start = MV78XX0_PCIE_MEM_PHYS_BASE;
for (i = 0; i < num_pcie_ports; i++) {
struct pcie_port *pp = pcie_port + i;
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
"PCIe %d.%d MEM", pp->maj, pp->min);
pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
pp->res.name = pp->mem_space_name;
pp->res.flags = IORESOURCE_MEM;
pp->res.start = start;
pp->res.end = start + size_each - 1;
start += size_each;
if (request_resource(&iomem_resource, &pp->res))
panic("can't allocate PCIe MEM sub-space");
mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
resource_size(&pp->res),
pp->maj, pp->min);
mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
pp->maj, pp->min);
}
}
static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
{
struct pcie_port *pp;
if (nr >= num_pcie_ports)
return 0;
pp = &pcie_port[nr];
sys->private_data = pp;
pp->root_bus_nr = sys->busnr;
/*
* Generic PCIe unit setup.
*/
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
orion_pcie_setup(pp->base);
pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
return 1;
}
static void __init mv78xx0_pcie_preinit(void)
{
int i;
u32 size_each;
u32 start;
int win;
pcie_io_space.name = "PCIe I/O Space";
pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
pcie_io_space.end =
MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
pcie_io_space.flags = IORESOURCE_IO;
if (request_resource(&iomem_resource, &pcie_io_space))
panic("can't allocate PCIe I/O space");
pcie_mem_space.name = "PCIe MEM Space";
pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
pcie_mem_space.end =
MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
pcie_mem_space.flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource, &pcie_mem_space))
panic("can't allocate PCIe MEM space");
for (i = 0; i < num_pcie_ports; i++) {
struct pcie_port *pp = pcie_port + i;
snprintf(pp->io_space_name, sizeof(pp->io_space_name),
"PCIe %d.%d I/O", pp->maj, pp->min);
pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
pp->res[0].name = pp->io_space_name;
pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
pp->res[0].flags = IORESOURCE_IO;
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
"PCIe %d.%d MEM", pp->maj, pp->min);
pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
pp->res[1].name = pp->mem_space_name;
pp->res[1].flags = IORESOURCE_MEM;
}
switch (num_pcie_ports) {
case 0:
size_each = 0;
break;
case 1:
size_each = 0x30000000;
break;
case 2 ... 3:
size_each = 0x10000000;
break;
case 4 ... 6:
size_each = 0x08000000;
break;
case 7:
size_each = 0x04000000;
break;
default:
panic("invalid number of PCIe ports");
}
start = MV78XX0_PCIE_MEM_PHYS_BASE;
for (i = 0; i < num_pcie_ports; i++) {
struct pcie_port *pp = pcie_port + i;
pp->res[1].start = start;
pp->res[1].end = start + size_each - 1;
start += size_each;
}
for (i = 0; i < num_pcie_ports; i++) {
struct pcie_port *pp = pcie_port + i;
if (request_resource(&pcie_io_space, &pp->res[0]))
panic("can't allocate PCIe I/O sub-space");
if (request_resource(&pcie_mem_space, &pp->res[1]))
panic("can't allocate PCIe MEM sub-space");
}
win = 0;
for (i = 0; i < num_pcie_ports; i++) {
struct pcie_port *pp = pcie_port + i;
mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
resource_size(&pp->res[0]),
pp->maj, pp->min);
mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
resource_size(&pp->res[1]),
pp->maj, pp->min);
}
}
