Esempio n. 1
0
static void mxr_reg_sub_mxr_reset(struct mxr_device *mdev, int mxr_num)
{
	u32 val; /* value stored to register */

	if (mxr_num == MXR_SUB_MIXER0) {
		/* setting default layer priority: layer1 > video > layer0
		 * because typical usage scenario would be
		 * layer0 - framebuffer
		 * video - video overlay
		 * layer1 - OSD
		 */
		val  = MXR_LAYER_CFG_GRP0_VAL(1);
		val |= MXR_LAYER_CFG_VP_VAL(2);
		val |= MXR_LAYER_CFG_GRP1_VAL(3);
		mxr_write(mdev, MXR_LAYER_CFG, val);

		/* use dark gray background color */
		mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
		mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
		mxr_write(mdev, MXR_BG_COLOR2, 0x008080);

		/* setting graphical layers */

		val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
		val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */
		val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */

		/* the same configuration for both layers */
		mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
		mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
	} else if (mxr_num == MXR_SUB_MIXER1) {
		val  = MXR_LAYER_CFG_GRP0_VAL(1);
		val |= MXR_LAYER_CFG_VP_VAL(2);
		val |= MXR_LAYER_CFG_GRP1_VAL(3);
		mxr_write(mdev, MXR1_LAYER_CFG, val);

		/* use dark gray background color */
		mxr_write(mdev, MXR1_BG_COLOR0, 0x008080);
		mxr_write(mdev, MXR1_BG_COLOR1, 0x008080);
		mxr_write(mdev, MXR1_BG_COLOR2, 0x008080);

		/* setting graphical layers */

		val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
		val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */
		val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */

		/* the same configuration for both layers */
		mxr_write(mdev, MXR1_GRAPHIC_CFG(0), val);
		mxr_write(mdev, MXR1_GRAPHIC_CFG(1), val);
	}
}
Esempio n. 2
0
void mxr_reg_reset(struct mxr_device *mdev)
{
	unsigned long flags;
	u32 val; /* value stored to register */

	spin_lock_irqsave(&mdev->reg_slock, flags);
	mxr_vsync_set_update(mdev, MXR_DISABLE);

	/* set output in RGB888 mode */
	mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);

	/* 16 beat burst in DMA */
	mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
		MXR_STATUS_BURST_MASK);

	/* setting default layer priority: layer1 > video > layer0
	 * because typical usage scenario would be
	 * layer0 - framebuffer
	 * video - video overlay
	 * layer1 - OSD
	 */
	val  = MXR_LAYER_CFG_GRP0_VAL(1);
	val |= MXR_LAYER_CFG_VP_VAL(2);
	val |= MXR_LAYER_CFG_GRP1_VAL(3);
	mxr_write(mdev, MXR_LAYER_CFG, val);

	/* use dark teal background color */
	mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
	mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
	mxr_write(mdev, MXR_BG_COLOR2, 0x008080);

	/* setting graphical layers */

	val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
	val |= MXR_GRP_CFG_LAYER_BLEND_EN;
	val &= ~MXR_GRP_CFG_BLEND_PRE_MUL; /* normal mode */
	val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */

	/* the same configuration for both layers */
	mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
	mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);

	/* configuration of Video Processor Registers */
	__mxr_reg_vp_reset(mdev);
	mxr_reg_vp_default_filter(mdev);

	/* enable all interrupts */
	mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);

	mxr_vsync_set_update(mdev, MXR_ENABLE);
	spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_set_layer_prio(struct mxr_device *mdev)
{
	u8 p_g0, p_g1, p_v;
	u32 val;

	p_v = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_VIDEO]->prio;
	p_g0 = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_GRP0]->prio;
	p_g1 = mdev->sub_mxr[MXR_SUB_MIXER0].layer[MXR_LAYER_GRP1]->prio;
	mxr_dbg(mdev, "video layer priority = %d\n", p_v);
	mxr_dbg(mdev, "graphic0 layer priority = %d\n", p_g0);
	mxr_dbg(mdev, "graphic1 layer priority = %d\n", p_g1);

	val  = MXR_LAYER_CFG_GRP1_VAL(p_g1);
	val |= MXR_LAYER_CFG_GRP0_VAL(p_g0);
	val |= MXR_LAYER_CFG_VP_VAL(p_v);
	mxr_write(mdev, MXR_LAYER_CFG, val);
}
void mxr_reg_reset(struct mxr_device *mdev)
{
	unsigned long flags;
	u32 val; 

	spin_lock_irqsave(&mdev->reg_slock, flags);
	mxr_vsync_set_update(mdev, MXR_DISABLE);

	
	mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);

	
	mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
		MXR_STATUS_BURST_MASK);

	val  = MXR_LAYER_CFG_GRP0_VAL(1);
	val |= MXR_LAYER_CFG_VP_VAL(2);
	val |= MXR_LAYER_CFG_GRP1_VAL(3);
	mxr_write(mdev, MXR_LAYER_CFG, val);

	
	mxr_write(mdev, MXR_BG_COLOR0, 0x808080);
	mxr_write(mdev, MXR_BG_COLOR1, 0x808080);
	mxr_write(mdev, MXR_BG_COLOR2, 0x808080);

	

	val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; 
	val |= MXR_GRP_CFG_BLEND_PRE_MUL; 
	val |= MXR_GRP_CFG_ALPHA_VAL(0xff); 

	
	mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
	mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);

	
	__mxr_reg_vp_reset(mdev);
	mxr_reg_vp_default_filter(mdev);

	
	mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);

	mxr_vsync_set_update(mdev, MXR_ENABLE);
	spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
static void mxr_reg_sub_mxr_reset(struct mxr_device *mdev, int mxr_num)
{
	u32 val; /* value stored to register */

	if (mxr_num == MXR_SUB_MIXER0) {
		/* use dark gray background color */
		mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
		mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
		mxr_write(mdev, MXR_BG_COLOR2, 0x008080);

		/* setting graphical layers */

		val  = MXR_GRP_CFG_BLANK_KEY_EN; /* no blank key */
		val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */

		/* the same configuration for both layers */
		mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
		mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
	} else if (mxr_num == MXR_SUB_MIXER1) {
		val  = MXR_LAYER_CFG_GRP1_VAL(3);
		val |= MXR_LAYER_CFG_GRP0_VAL(2);
		val |= MXR_LAYER_CFG_VP_VAL(1);
		mxr_write(mdev, MXR1_LAYER_CFG, val);

		/* use dark gray background color */
		mxr_write(mdev, MXR1_BG_COLOR0, 0x008080);
		mxr_write(mdev, MXR1_BG_COLOR1, 0x008080);
		mxr_write(mdev, MXR1_BG_COLOR2, 0x008080);

		/* setting graphical layers */

		val  = MXR_GRP_CFG_BLANK_KEY_EN; /* no blank key */
		val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */

		/* the same configuration for both layers */
		mxr_write(mdev, MXR1_GRAPHIC_CFG(0), val);
		mxr_write(mdev, MXR1_GRAPHIC_CFG(1), val);
	}
}