STATIC
EFI_STATUS
ConfigureI2c (
VOID
)
{
//Program prescaler to obtain 12-MHz clock
MmioWrite16(I2C_PSC, 0x0000);
//Program SCLL and SCLH
//NOTE: Following values are the register dump after U-Boot code executed.
//We need to figure out how its calculated based on the I2C functional clock and I2C_PSC.
MmioWrite16(I2C_SCLL, 0x0035);
MmioWrite16(I2C_SCLH, 0x0035);
//Take the I2C controller out of reset.
MmioOr16(I2C_CON, I2C_EN);
//Initialize the I2C controller.
//Set I2C controller in Master mode.
MmioOr16(I2C_CON, MST);
//Enable interrupts for receive/transmit mode.
MmioOr16(I2C_IE, (XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE));
return EFI_SUCCESS;
}
/**
Override function for SDHCI controller operations
@param[in] ControllerHandle The EFI_HANDLE of the controller.
@param[in] Slot The 0 based slot index.
@param[in] PhaseType The type of operation and whether the
hook is invoked right before (pre) or
right after (post)
@retval EFI_SUCCESS The override function completed successfully.
@retval EFI_NOT_FOUND The specified controller or slot does not exist.
@retval EFI_INVALID_PARAMETER PhaseType is invalid
**/
STATIC
EFI_STATUS
EFIAPI
SynQuacerSdMmcNotifyPhase (
IN EFI_HANDLE ControllerHandle,
IN UINT8 Slot,
IN EDKII_SD_MMC_PHASE_TYPE PhaseType
)
{
if (ControllerHandle != mSdMmcControllerHandle) {
return EFI_SUCCESS;
}
ASSERT (Slot == 0);
switch (PhaseType) {
case EdkiiSdMmcResetPre:
// Soft reset does not complete unless the clock is already enabled.
MmioWrite16 (SYNQUACER_EMMC_BASE + SD_HC_CLOCK_CTRL,
SYNQUACER_CLOCK_CTRL_VAL);
break;
case EdkiiSdMmcInitHostPre:
// init vendor specific regs
MmioAnd16 (SYNQUACER_EMMC_BASE + F_SDH30_AHB_CONFIG,
~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN));
MmioOr16 (SYNQUACER_EMMC_BASE + F_SDH30_AHB_CONFIG,
F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
F_SDH30_AHB_INCR_4);
MmioAnd32 (SYNQUACER_EMMC_BASE + F_SDH30_ESD_CONTROL, ~F_SDH30_EMMC_RST);
MemoryFence ();
gBS->Stall (ESD_CONTROL_RESET_DELAY);
MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_ESD_CONTROL,
F_SDH30_EMMC_RST | F_SDH30_CMD_DAT_DELAY | F_SDH30_EMMC_HS200);
gBS->Stall (IO_CONTROL2_SETTLE_US);
MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, F_SDH30_CRES_O_DN);
MemoryFence ();
MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, F_SDH30_MSEL_O_1_8);
MemoryFence ();
MmioAnd32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, ~F_SDH30_CRES_O_DN);
MemoryFence ();
gBS->Stall (IO_CONTROL2_SETTLE_US);
MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_TUNING_SETTING,
F_SDH30_CMD_CHK_DIS);
break;
default:
break;
}
return EFI_SUCCESS;
}
/**
Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise inclusive OR between the read result and the value specified by
OrData, and writes the result to the 16-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
PciExpressOr16 (
IN UINTN Address,
IN UINT16 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
}
STATIC
EFI_STATUS
PollForStatus(
UINT16 StatusBit
)
{
UINTN Retry = 0;
while(Retry < MAX_RETRY) {
if (MmioRead16(I2C_STAT) & StatusBit) {
//Clear particular status bit from Status register.
MmioOr16(I2C_STAT, StatusBit);
break;
}
Retry++;
}
if (Retry == MAX_RETRY) {
return EFI_TIMEOUT;
}
return EFI_SUCCESS;
}
EFI_STATUS
SendSpiCmd (
IN EFI_SPI_PROTOCOL *This,
IN UINT8 OpcodeIndex,
IN UINT8 PrefixOpcodeIndex,
IN BOOLEAN DataCycle,
IN BOOLEAN Atomic,
IN BOOLEAN ShiftOut,
IN UINTN Address,
IN UINT32 DataByteCount,
IN OUT UINT8 *Buffer,
IN SPI_REGION_TYPE SpiRegionType
)
/*++
Routine Description:
This function sends the programmed SPI command to the slave device.
Arguments:
OpcodeIndex Index of the command in the OpCode Menu.
PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.
DataCycle TRUE if the SPI cycle contains data
Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.
ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.
Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform
Region, this value specifies the offset from the Region Base; for BIOS Region,
this value specifies the offset from the start of the BIOS Image. In Non
Descriptor Mode, this value specifies the offset from the start of the BIOS Image.
Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor
Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is
supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or
the flash (in Non Descriptor Mode)
DataByteCount Number of bytes in the data portion of the SPI cycle. This function may break the
data transfer into multiple operations. This function ensures each operation does
not cross 256 byte flash address boundary.
*NOTE: if there is some SPI chip that has a stricter address boundary requirement
(e.g., its write page size is < 256 byte), then the caller cannot rely on this
function to cut the data transfer at proper address boundaries, and it's the
caller's reponsibility to pass in a properly cut DataByteCount parameter.
Buffer Data received or sent during the SPI cycle.
SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,
EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in
Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode
and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative
to base of the 1st flash device (i.e., it is a Flash Linear Address).
Returns:
EFI_SUCCESS SPI command completes successfully.
EFI_DEVICE_ERROR Device error, the command aborts abnormally.
EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode
EFI_INVALID_PARAMETER The parameters specified are not valid.
--*/
{
UINT32 Index;
SPI_INSTANCE *SpiInstance;
UINTN HardwareSpiAddr;
UINTN SpiBiosSize;
UINTN BaseAddress;
UINTN LimitAddress;
UINT32 SpiDataCount;
UINT8 OpCode;
SPI_OPERATION Operation;
UINTN PchRootComplexBar;
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
PchRootComplexBar = SpiInstance->PchRootComplexBar;
SpiBiosSize = SpiInstance->SpiInitTable.BiosSize;
Operation = SpiInstance->SpiInitTable.OpcodeMenu[OpcodeIndex].Operation;
OpCode = MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + OpcodeIndex);
//
// Check if the value of opcode register is 0 or the BIOS Size of SpiInitTable is 0
//
if (OpCode == 0 || SpiBiosSize == 0) {
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
}
SpiOffset2Physical (This, Address, SpiRegionType, &HardwareSpiAddr, &BaseAddress, &LimitAddress);
//
// Have direct access to BIOS region in Descriptor mode,
//
if (SpiInstance->SpiInitTable.OpcodeMenu[OpcodeIndex].Type == EnumSpiOpcodeRead &&
SpiRegionType == EnumSpiRegionBios) {
CopyMem (
Buffer,
(UINT8 *) ((HardwareSpiAddr - BaseAddress) + (UINT32) (~(SpiBiosSize - 1))),
DataByteCount
);
return EFI_SUCCESS;
}
//
// DEBUG((EFI_D_ERROR, "SPIADDR %x, %x, %x, %x\n", Address, HardwareSpiAddr, BaseAddress,
// LimitAddress));
//
if ((DataCycle == FALSE) && (DataByteCount > 0)) {
DataByteCount = 0;
}
do {
//
// Trim at 256 byte boundary per operation,
// - PCH SPI controller requires trimming at 4KB boundary
// - Some SPI chips require trimming at 256 byte boundary for write operation
// - Trimming has limited performance impact as we can read / write atmost 64 byte
// per operation
//
if (HardwareSpiAddr + DataByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
} else {
SpiDataCount = DataByteCount;
}
//
// Calculate the number of bytes to shift in/out during the SPI data cycle.
// Valid settings for the number of bytes duing each data portion of the
// PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
//
if (SpiDataCount >= 64) {
SpiDataCount = 64;
} else if ((SpiDataCount &~0x07) != 0) {
SpiDataCount = SpiDataCount &~0x07;
}
//
// If shifts data out, load data into the SPI data buffer.
//
if (ShiftOut) {
for (Index = 0; Index < SpiDataCount; Index++) {
MmioWrite8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index, Buffer[Index]);
MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index);
}
}
MmioWrite32 (
(PchRootComplexBar + R_QNC_RCRB_SPIA),
(UINT32) (HardwareSpiAddr & B_QNC_RCRB_SPIA_MASK)
);
MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIA);
//
// Execute the command on the SPI compatible mode
//
//
// Clear error flags
//
MmioOr16 ((PchRootComplexBar + R_QNC_RCRB_SPIS), B_QNC_RCRB_SPIS_BAS);
//
// Initialte the SPI cycle
//
if (DataCycle) {
MmioWrite16 (
(PchRootComplexBar + R_QNC_RCRB_SPIC),
( (UINT16) (B_QNC_RCRB_SPIC_DC) | (UINT16) (((SpiDataCount - 1) << 8) & B_QNC_RCRB_SPIC_DBC) |
(UINT16) ((OpcodeIndex << 4) & B_QNC_RCRB_SPIC_COP) |
(UINT16) ((PrefixOpcodeIndex << 3) & B_QNC_RCRB_SPIC_SPOP) |
(UINT16) (Atomic ? B_QNC_RCRB_SPIC_ACS : 0) |
(UINT16) (B_QNC_RCRB_SPIC_SCGO)));
} else {
MmioWrite16 (
(PchRootComplexBar + R_QNC_RCRB_SPIC),
( (UINT16) ((OpcodeIndex << 4) & B_QNC_RCRB_SPIC_COP) |
(UINT16) ((PrefixOpcodeIndex << 3) & B_QNC_RCRB_SPIC_SPOP) |
(UINT16) (Atomic ? B_QNC_RCRB_SPIC_ACS : 0) |
(UINT16) (B_QNC_RCRB_SPIC_SCGO)));
}
MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIC);
//
// end of command execution
//
// Wait the SPI cycle to complete.
//
if (!WaitForSpiCycleComplete (This, TRUE)) {
return EFI_DEVICE_ERROR;
}
//
// If shifts data in, get data from the SPI data buffer.
//
if (!ShiftOut) {
for (Index = 0; Index < SpiDataCount; Index++) {
Buffer[Index] = MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPID0 + Index);
}
}
HardwareSpiAddr += SpiDataCount;
Buffer += SpiDataCount;
DataByteCount -= SpiDataCount;
} while (DataByteCount > 0);
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
SpiProtocolLock (
IN EFI_SPI_PROTOCOL *This
)
/*++
Routine Description:
Lock the SPI Static Configuration Interface.
Once locked, the interface can not be changed and can only be clear by system reset.
Arguments:
This Pointer to the EFI_SPI_PROTOCOL instance.
Returns:
EFI_SUCCESS Lock operation succeed.
EFI_DEVICE_ERROR Device error, operation failed.
EFI_ACCESS_DENIED The interface has already been locked.
--*/
{
SPI_INSTANCE *SpiInstance;
UINTN PchRootComplexBar;
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
PchRootComplexBar = SpiInstance->PchRootComplexBar;
//
// Check if the SPI interface has been locked-down.
//
if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {
return EFI_ACCESS_DENIED;
}
//
// Lock-down the configuration interface.
//
MmioOr16 ((UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS), (UINT16) (B_QNC_RCRB_SPIS_SCL));
//
// Verify if it's really locked.
//
if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) == 0) {
return EFI_DEVICE_ERROR;
} else {
//
// Save updated register in S3 Boot script.
//
S3BootScriptSaveMemWrite (
S3BootScriptWidthUint16,
(UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS),
1,
(VOID *) (UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS)
);
}
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
SpiProtocolInit (
IN EFI_SPI_PROTOCOL *This,
IN SPI_INIT_TABLE *InitTable
)
/*++
Routine Description:
Initialize the host controller to execute SPI command.
Arguments:
This Pointer to the EFI_SPI_PROTOCOL instance.
InitTable Initialization data to be programmed into the SPI host controller.
Returns:
EFI_SUCCESS Initialization completed.
EFI_ACCESS_DENIED The SPI static configuration interface has been locked-down.
EFI_INVALID_PARAMETER Bad input parameters.
EFI_UNSUPPORTED Can't get Descriptor mode VSCC values
--*/
{
EFI_STATUS Status;
UINT8 Index;
UINT16 OpcodeType;
SPI_INSTANCE *SpiInstance;
BOOLEAN MultiPartitionIsSupported;
UINTN PchRootComplexBar;
UINT8 SFDPCmdOpcodeIndex;
UINT8 UnlockCmdOpcodeIndex;
UINT8 ReadDataCmdOpcodeIndex;
UINT8 FlashPartId[3];
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
PchRootComplexBar = SpiInstance->PchRootComplexBar;
if (InitTable != NULL) {
//
// Copy table into SPI driver Private data structure
//
CopyMem (
&SpiInstance->SpiInitTable,
InitTable,
sizeof (SPI_INIT_TABLE)
);
} else {
return EFI_INVALID_PARAMETER;
}
//
// Check if the SPI interface has been locked-down.
//
if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {
ASSERT_EFI_ERROR (EFI_ACCESS_DENIED);
return EFI_ACCESS_DENIED;
}
//
// Clear all the status bits for status regs.
//
MmioOr16 (
(UINTN) (PchRootComplexBar + R_QNC_RCRB_SPIS),
(UINT16) ((B_QNC_RCRB_SPIS_CDS | B_QNC_RCRB_SPIS_BAS))
);
MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS);
//
// Set the Prefix Opcode registers.
//
MmioWrite16 (
PchRootComplexBar + R_QNC_RCRB_SPIPREOP,
(SpiInstance->SpiInitTable.PrefixOpcode[1] << 8) | InitTable->PrefixOpcode[0]
);
MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIPREOP);
//
// Set Opcode Type Configuration registers.
//
for (Index = 0, OpcodeType = 0; Index < SPI_NUM_OPCODE; Index++) {
switch (SpiInstance->SpiInitTable.OpcodeMenu[Index].Type) {
case EnumSpiOpcodeRead:
OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_ADD_READ << (Index * 2));
break;
case EnumSpiOpcodeWrite:
OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_ADD_WRITE << (Index * 2));
break;
case EnumSpiOpcodeWriteNoAddr:
OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE << (Index * 2));
break;
default:
OpcodeType |= (UINT16) (B_QNC_RCRB_SPIOPTYPE_NOADD_READ << (Index * 2));
break;
}
}
MmioWrite16 (PchRootComplexBar + R_QNC_RCRB_SPIOPTYPE, OpcodeType);
MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIOPTYPE);
//
// Setup the Opcode Menu registers.
//
ReadDataCmdOpcodeIndex = SPI_NUM_OPCODE;
SFDPCmdOpcodeIndex = SPI_NUM_OPCODE;
UnlockCmdOpcodeIndex = SPI_NUM_OPCODE;
for (Index = 0; Index < SPI_NUM_OPCODE; Index++) {
MmioWrite8 (
PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + Index,
SpiInstance->SpiInitTable.OpcodeMenu[Index].Code
);
MmioRead8 (PchRootComplexBar + R_QNC_RCRB_SPIOPMENU + Index);
if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationJedecId) {
Status = SpiProtocolExecute (
This,
Index,
0,
TRUE,
TRUE,
FALSE,
(UINTN) 0,
3,
FlashPartId,
EnumSpiRegionDescriptor
);
if (EFI_ERROR (Status)) {
return Status;
}
if (FlashPartId[0] != SpiInstance->SpiInitTable.VendorId ||
FlashPartId[1] != SpiInstance->SpiInitTable.DeviceId0 ||
FlashPartId[2] != SpiInstance->SpiInitTable.DeviceId1) {
return EFI_INVALID_PARAMETER;
}
}
if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationReadData ||
SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationFastRead ||
SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationDualOutputFastRead) {
ReadDataCmdOpcodeIndex = Index;
}
if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationDiscoveryParameters) {
SFDPCmdOpcodeIndex = Index;
}
if (SpiInstance->SpiInitTable.OpcodeMenu[Index].Operation == EnumSpiOperationWriteStatus) {
UnlockCmdOpcodeIndex = Index;
}
}
MultiPartitionIsSupported = FALSE;
Status = UnlockFlashComponents (
This,
UnlockCmdOpcodeIndex
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "Unlock flash components fail!\n"));
}
SpiPhaseInit ();
FillOutPublicInfoStruct (SpiInstance);
SpiInstance->InitDone = TRUE;
return EFI_SUCCESS;
}
