void ni_tio_init_counter(struct ni_gpct *counter)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
ni_tio_reset_count_and_disarm(counter);
/* initialize counter registers */
counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] =
0x0;
write_register(counter,
counter_dev->
regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)],
NITIO_Gi_Autoincrement_Reg(counter->counter_index));
ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
~0, Gi_Synchronize_Gate_Bit);
ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0,
0);
counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
write_register(counter,
counter_dev->
regs[NITIO_Gi_LoadA_Reg(counter->counter_index)],
NITIO_Gi_LoadA_Reg(counter->counter_index));
counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0;
write_register(counter,
counter_dev->
regs[NITIO_Gi_LoadB_Reg(counter->counter_index)],
NITIO_Gi_LoadB_Reg(counter->counter_index));
ni_tio_set_bits(counter,
NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0,
0);
if (ni_tio_counting_mode_registers_present(counter_dev)) {
ni_tio_set_bits(counter,
NITIO_Gi_Counting_Mode_Reg(counter->
counter_index), ~0,
0);
}
if (ni_tio_second_gate_registers_present(counter_dev)) {
counter_dev->
regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)] =
0x0;
write_register(counter,
counter_dev->
regs[NITIO_Gi_Second_Gate_Reg
(counter->counter_index)],
NITIO_Gi_Second_Gate_Reg(counter->
counter_index));
}
ni_tio_set_bits(counter,
NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0,
0x0);
ni_tio_set_bits(counter,
NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
~0, 0x0);
}
static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
unsigned int gate_source)
{
const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
unsigned mode_values = 0;
if (gate_source & CR_INVERT)
mode_values |= Gi_Gate_Polarity_Bit;
if (gate_source & CR_EDGE)
mode_values |= Gi_Rising_Edge_Gating_Bits;
else
mode_values |= Gi_Level_Gating_Bits;
ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
mode_mask, mode_values);
}
void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, int *gate_error,
int *tc_error, int *perm_stale_data, int *stale_data)
{
const unsigned short gxx_status = read_register(counter,
NITIO_Gxx_Status_Reg(counter->counter_index));
const unsigned short gi_status = read_register(counter,
NITIO_Gi_Status_Reg(counter->counter_index));
unsigned ack = 0;
if (gate_error)
*gate_error = 0;
if (tc_error)
*tc_error = 0;
if (perm_stale_data)
*perm_stale_data = 0;
if (stale_data)
*stale_data = 0;
if (gxx_status & Gi_Gate_Error_Bit(counter->counter_index)) {
ack |= Gi_Gate_Error_Confirm_Bit(counter->counter_index);
if (gate_error) {
/*660x don't support automatic acknowledgement of gate interrupt via dma read/write
and report bogus gate errors */
if (counter->counter_dev->variant !=
ni_gpct_variant_660x) {
*gate_error = 1;
}
}
}
if (gxx_status & Gi_TC_Error_Bit(counter->counter_index)) {
ack |= Gi_TC_Error_Confirm_Bit(counter->counter_index);
if (tc_error)
*tc_error = 1;
}
if (gi_status & Gi_TC_Bit) {
ack |= Gi_TC_Interrupt_Ack_Bit;
}
if (gi_status & Gi_Gate_Interrupt_Bit) {
if (should_ack_gate(counter))
ack |= Gi_Gate_Interrupt_Ack_Bit;
}
if (ack)
write_register(counter, ack,
NITIO_Gi_Interrupt_Acknowledge_Reg(counter->
counter_index));
if (ni_tio_get_soft_copy(counter,
NITIO_Gi_Mode_Reg(counter->
counter_index)) & Gi_Loading_On_Gate_Bit) {
if (gxx_status & Gi_Stale_Data_Bit(counter->counter_index)) {
if (stale_data)
*stale_data = 1;
}
if (read_register(counter,
NITIO_Gxx_Joint_Status2_Reg(counter->
counter_index)) &
Gi_Permanent_Stale_Bit(counter->counter_index)) {
rt_printk("%s: Gi_Permanent_Stale_Data detected.\n",
__FUNCTION__);
if (perm_stale_data)
*perm_stale_data = 1;
}
}
}
static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned mode_reg_mask;
unsigned mode_reg_values;
unsigned input_select_bits = 0;
/* these bits map directly on to the mode register */
static const unsigned mode_reg_direct_mask =
NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
mode_reg_values = mode & mode_reg_direct_mask;
switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
break;
case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
mode_reg_values |= Gi_Reload_Source_Switching_Bit;
break;
case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
mode_reg_mask |= Gi_Gating_Mode_Mask;
mode_reg_values |= Gi_Level_Gating_Bits;
break;
default:
break;
}
ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
mode_reg_mask, mode_reg_values);
if (ni_tio_counting_mode_registers_present(counter_dev)) {
unsigned counting_mode_bits = 0;
counting_mode_bits |=
(mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
Gi_Counting_Mode_Mask;
counting_mode_bits |=
((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
if (mode & NI_GPCT_INDEX_ENABLE_BIT) {
counting_mode_bits |= Gi_Index_Mode_Bit;
}
ni_tio_set_bits(counter,
NITIO_Gi_Counting_Mode_Reg(counter->counter_index),
Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
Gi_Index_Mode_Bit, counting_mode_bits);
ni_tio_set_sync_mode(counter, 0);
}
ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
Gi_Up_Down_Mask,
(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) << Gi_Up_Down_Shift);
if (mode & NI_GPCT_OR_GATE_BIT) {
input_select_bits |= Gi_Or_Gate_Bit;
}
if (mode & NI_GPCT_INVERT_OUTPUT_BIT) {
input_select_bits |= Gi_Output_Polarity_Bit;
}
ni_tio_set_bits(counter,
NITIO_Gi_Input_Select_Reg(counter->counter_index),
Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
Gi_Output_Polarity_Bit, input_select_bits);
return 0;
}
static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
lsampl_t * gate_source)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
const unsigned mode_bits = ni_tio_get_soft_copy(counter,
NITIO_Gi_Mode_Reg(counter->counter_index));
const unsigned second_gate_reg =
NITIO_Gi_Second_Gate_Reg(counter->counter_index);
unsigned gate_select_bits;
switch (gate_index) {
case 0:
if ((mode_bits & Gi_Gating_Mode_Mask) ==
Gi_Gating_Disabled_Bits) {
*gate_source = NI_GPCT_DISABLED_GATE_SELECT;
return 0;
} else {
gate_select_bits =
(ni_tio_get_soft_copy(counter,
NITIO_Gi_Input_Select_Reg(counter->
counter_index)) &
Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
}
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
*gate_source =
ni_m_series_first_gate_to_generic_gate_source
(gate_select_bits);
break;
case ni_gpct_variant_660x:
*gate_source =
ni_660x_first_gate_to_generic_gate_source
(gate_select_bits);
break;
default:
BUG();
break;
}
if (mode_bits & Gi_Gate_Polarity_Bit) {
*gate_source |= CR_INVERT;
}
if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits) {
*gate_source |= CR_EDGE;
}
break;
case 1:
if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
|| (counter_dev->
regs[second_gate_reg] & Gi_Second_Gate_Mode_Bit)
== 0) {
*gate_source = NI_GPCT_DISABLED_GATE_SELECT;
return 0;
} else {
gate_select_bits =
(counter_dev->
regs[second_gate_reg] &
Gi_Second_Gate_Select_Mask) >>
Gi_Second_Gate_Select_Shift;
}
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
*gate_source =
ni_m_series_second_gate_to_generic_gate_source
(gate_select_bits);
break;
case ni_gpct_variant_660x:
*gate_source =
ni_660x_second_gate_to_generic_gate_source
(gate_select_bits);
break;
default:
BUG();
break;
}
if (counter_dev->
regs[second_gate_reg] & Gi_Second_Gate_Polarity_Bit) {
*gate_source |= CR_INVERT;
}
/* second gate can't have edge/level mode set independently */
if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits) {
*gate_source |= CR_EDGE;
}
break;
default:
return -EINVAL;
break;
}
return 0;
}
int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
lsampl_t gate_source)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
const unsigned second_gate_reg =
NITIO_Gi_Second_Gate_Reg(counter->counter_index);
switch (gate_index) {
case 0:
if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
ni_tio_set_bits(counter,
NITIO_Gi_Mode_Reg(counter->counter_index),
Gi_Gating_Mode_Mask, Gi_Gating_Disabled_Bits);
return 0;
}
ni_tio_set_first_gate_modifiers(counter, gate_source);
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
return ni_m_series_set_first_gate(counter, gate_source);
break;
case ni_gpct_variant_660x:
return ni_660x_set_first_gate(counter, gate_source);
break;
default:
BUG();
break;
}
break;
case 1:
if (ni_tio_second_gate_registers_present(counter_dev) == 0)
return -EINVAL;
if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
counter_dev->regs[second_gate_reg] &=
~Gi_Second_Gate_Mode_Bit;
write_register(counter,
counter_dev->regs[second_gate_reg],
second_gate_reg);
return 0;
}
if (gate_source & CR_INVERT) {
counter_dev->regs[second_gate_reg] |=
Gi_Second_Gate_Polarity_Bit;
} else {
counter_dev->regs[second_gate_reg] &=
~Gi_Second_Gate_Polarity_Bit;
}
switch (counter_dev->variant) {
case ni_gpct_variant_m_series:
return ni_m_series_set_second_gate(counter,
gate_source);
break;
case ni_gpct_variant_660x:
return ni_660x_set_second_gate(counter, gate_source);
break;
default:
BUG();
break;
}
break;
default:
return -EINVAL;
break;
}
return 0;
}
void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, int *gate_error,
int *tc_error, int *perm_stale_data,
int *stale_data)
{
const unsigned short gxx_status = read_register(counter,
NITIO_Gxx_Status_Reg
(counter->
counter_index));
const unsigned short gi_status = read_register(counter,
NITIO_Gi_Status_Reg
(counter->
counter_index));
unsigned ack = 0;
if (gate_error)
*gate_error = 0;
if (tc_error)
*tc_error = 0;
if (perm_stale_data)
*perm_stale_data = 0;
if (stale_data)
*stale_data = 0;
if (gxx_status & Gi_Gate_Error_Bit(counter->counter_index)) {
ack |= Gi_Gate_Error_Confirm_Bit(counter->counter_index);
if (gate_error) {
if (counter->counter_dev->variant !=
ni_gpct_variant_660x) {
*gate_error = 1;
}
}
}
if (gxx_status & Gi_TC_Error_Bit(counter->counter_index)) {
ack |= Gi_TC_Error_Confirm_Bit(counter->counter_index);
if (tc_error)
*tc_error = 1;
}
if (gi_status & Gi_TC_Bit)
ack |= Gi_TC_Interrupt_Ack_Bit;
if (gi_status & Gi_Gate_Interrupt_Bit) {
if (should_ack_gate(counter))
ack |= Gi_Gate_Interrupt_Ack_Bit;
}
if (ack)
write_register(counter, ack,
NITIO_Gi_Interrupt_Acknowledge_Reg
(counter->counter_index));
if (ni_tio_get_soft_copy
(counter,
NITIO_Gi_Mode_Reg(counter->counter_index)) &
Gi_Loading_On_Gate_Bit) {
if (gxx_status & Gi_Stale_Data_Bit(counter->counter_index)) {
if (stale_data)
*stale_data = 1;
}
if (read_register(counter,
NITIO_Gxx_Joint_Status2_Reg
(counter->counter_index)) &
Gi_Permanent_Stale_Bit(counter->counter_index)) {
printk(KERN_INFO "%s: Gi_Permanent_Stale_Data detected.\n",
__func__);
if (perm_stale_data)
*perm_stale_data = 1;
}
}
}
