ATTR_HOT inline void NETLIB_NAME(7474sub)::newstate(const UINT8 stateQ, const UINT8 stateQQ)
{
// 0: High-to-low 40 ns, 1: Low-to-high 25 ns
static const netlist_time delay[2] = { NLTIME_FROM_NS(40), NLTIME_FROM_NS(25) };
OUTLOGIC(m_Q, stateQ, delay[stateQ]);
OUTLOGIC(m_QQ, stateQQ, delay[stateQQ]);
}
ATTR_HOT ATTR_ALIGN void netlist_base_t::process_queue(const netlist_time delta)
{
m_stop = m_time + delta;
if (m_mainclock == NULL)
{
while ( (m_time < m_stop) && (m_queue.is_not_empty()))
{
const netlist_queue_t::entry_t &e = m_queue.pop();
m_time = e.time();
e.object()->update_devs();
add_to_stat(m_perf_out_processed, 1);
if (FATAL_ERROR_AFTER_NS)
if (time() > NLTIME_FROM_NS(FATAL_ERROR_AFTER_NS))
error("Stopped");
}
if (m_queue.is_empty())
m_time = m_stop;
} else {
netlist_net_t &mcQ = m_mainclock->m_Q.net();
const netlist_time inc = m_mainclock->m_inc;
while (m_time < m_stop)
{
if (m_queue.is_not_empty())
{
while (m_queue.peek().time() > mcQ.time())
{
m_time = mcQ.time();
NETLIB_NAME(mainclock)::mc_update(mcQ, m_time + inc);
}
const netlist_queue_t::entry_t &e = m_queue.pop();
m_time = e.time();
e.object()->update_devs();
} else {
m_time = mcQ.time();
NETLIB_NAME(mainclock)::mc_update(mcQ, m_time + inc);
}
if (FATAL_ERROR_AFTER_NS)
if (time() > NLTIME_FROM_NS(FATAL_ERROR_AFTER_NS))
error("Stopped");
add_to_stat(m_perf_out_processed, 1);
}
}
}
ATTR_HOT void nld_d_to_a_proxy::update()
{
const int state = INPLOGIC(m_I);
if (state != m_last_state)
{
m_last_state = state;
const nl_double R = state ? logic_family().m_R_high : logic_family().m_R_low;
const nl_double V = state ? logic_family().m_high_V : logic_family().m_low_V;
// We only need to update the net first if this is a time stepping net
if (m_is_timestep)
{
m_RV.update_dev();
}
m_RV.set(NL_FCONST(1.0) / R, V, 0.0);
m_RV.m_P.schedule_after(NLTIME_FROM_NS(1));
}
}
* nld_82S16.c
*
*/
#include "nld_82S16.h"
NETLIB_NAMESPACE_DEVICES_START()
// FIXME: timing!
// FIXME: optimize device (separate address decoder!)
NETLIB_UPDATE(82S16)
{
if (INPLOGIC(m_CE1Q) || INPLOGIC(m_CE2Q) || INPLOGIC(m_CE3Q))
{
// FIXME: Outputs are tristate. This needs to be properly implemented
OUTLOGIC(m_DOUTQ, 1, NLTIME_FROM_NS(20));
//for (int i=0; i<8; i++)
//m_A[i].inactivate();
}
else
{
unsigned int adr = 0;
for (int i=0; i<8; i++)
{
//m_A[i].activate();
adr |= (INPLOGIC(m_A[i]) << i);
}
if (!INPLOGIC(m_WEQ))
{
m_ram[adr >> 6] = (m_ram[adr >> 6] & ~((UINT64) 1 << (adr & 0x3f))) | ((UINT64) INPLOGIC(m_DIN) << (adr & 0x3f));
{
m_sub.m_cnt = 0;
m_sub.m_IP.inactivate();
/* static */ const netlist_time reset_time = netlist_time::from_nsec(140);
m_sub.m_Q[0].push(0, reset_time);
for (std::size_t i=3; i<14; i++)
m_sub.m_Q[i].push(0, reset_time);
}
else
m_sub.m_IP.activate_hl();
}
inline NETLIB_FUNC_VOID(CD4020_sub, update_outputs, (const unsigned cnt))
{
/* static */ const netlist_time out_delayQn[14] = {
NLTIME_FROM_NS(180), NLTIME_FROM_NS(280),
NLTIME_FROM_NS(380), NLTIME_FROM_NS(480),
NLTIME_FROM_NS(580), NLTIME_FROM_NS(680),
NLTIME_FROM_NS(780), NLTIME_FROM_NS(880),
NLTIME_FROM_NS(980), NLTIME_FROM_NS(1080),
NLTIME_FROM_NS(1180), NLTIME_FROM_NS(1280),
NLTIME_FROM_NS(1380), NLTIME_FROM_NS(1480),
};
m_Q[0].push(cnt & 1, out_delayQn[0]);
for (std::size_t i=3; i<14; i++)
m_Q[i].push((cnt >> i) & 1, out_delayQn[i]);
}
NETLIB_DEVICE_IMPL(CD4020)
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_74175.c
*
*/
#include "nld_74175.h"
NETLIB_NAMESPACE_DEVICES_START()
static const netlist_time delay[2] = { NLTIME_FROM_NS(25), NLTIME_FROM_NS(25) };
static const netlist_time delay_clear[2] = { NLTIME_FROM_NS(40), NLTIME_FROM_NS(25) };
NETLIB_START(74175_sub)
{
register_input("CLK", m_CLK);
register_output("Q1", m_Q[0]);
register_output("Q1Q", m_QQ[0]);
register_output("Q2", m_Q[1]);
register_output("Q2Q", m_QQ[1]);
register_output("Q3", m_Q[2]);
register_output("Q3Q", m_QQ[2]);
register_output("Q4", m_Q[3]);
register_output("Q4Q", m_QQ[3]);
save(NLNAME(m_clrq));
save(NLNAME(m_data));
}
/*
* nld_82S16.c
*
*/
#include "nld_82S16.h"
static const netlist_time delay[2] = { NLTIME_FROM_NS(40), NLTIME_FROM_NS(25) };
// FIXME: timing!
// FIXME: optimize device (separate address decoder!)
NETLIB_UPDATE(82S16)
{
if (INPLOGIC(m_CE1Q) || INPLOGIC(m_CE2Q) || INPLOGIC(m_CE3Q))
{
// FIXME: Outputs are tristate. This needs to be properly implemented
OUTLOGIC(m_DOUTQ, 1, NLTIME_FROM_NS(40));
}
else
{
int adr = 0;
for (int i=0; i<8; i++)
adr |= (INPLOGIC(m_A[i]) << i);
if (!INPLOGIC(m_WEQ))
{
m_ram[adr] = INPLOGIC(m_DIN);
}
OUTLOGIC(m_DOUTQ, m_ram[adr] ^ 1, NLTIME_FROM_NS(40));
}
}
* nld_74123.c
*
*/
#include "nld_74123.h"
#define R_OFF (1E20)
#define R_ON (m_RI.Value())
NETLIB_NAMESPACE_DEVICES_START()
NETLIB_UPDATE(74123)
{
netlist_sig_t m_trig;
netlist_sig_t res = !INPLOGIC(m_CLRQ);
netlist_time t_AB_to_Q = NLTIME_FROM_NS(10);
netlist_time t_C_to_Q = NLTIME_FROM_NS(10);
if (m_dev_type == 74123)
{
m_trig = (INPLOGIC(m_A) ^ 1) & INPLOGIC(m_B) & INPLOGIC(m_CLRQ);
}
else if (m_dev_type == 9602)
{
m_trig = (INPLOGIC(m_A) ^ 1) | INPLOGIC(m_B);
}
else // 4538
{
m_trig = (INPLOGIC(m_B) ^ 1) | INPLOGIC(m_A);
// The line below is from the datasheet truthtable ... doesn't make sense at all
//res = res | INPLOGIC(m_A) | (INPLOGIC(m_B) ^ 1);
