int serial_init (void) { int clock_divisor; #ifdef CFG_NS87308 initialise_ns87308(); #endif #ifdef CFG_NS16550_COM1 clock_divisor = calc_divisor(serial_ports[0]); NS16550_init(serial_ports[0], clock_divisor); #endif #ifdef CFG_NS16550_COM2 clock_divisor = calc_divisor(serial_ports[1]); NS16550_init(serial_ports[1], clock_divisor); #endif #ifdef CFG_NS16550_COM3 clock_divisor = calc_divisor(serial_ports[2]); NS16550_init(serial_ports[2], clock_divisor); #endif #ifdef CFG_NS16550_COM4 clock_divisor = calc_divisor(serial_ports[3]); NS16550_init(serial_ports[3], clock_divisor); #endif return (0); }
static int marvell_serial_init(void) { int clock_divisor = 230400 / gd->baudrate; #ifdef CONFIG_SYS_INIT_CHAN1 (void) NS16550_init (0, clock_divisor); #endif #ifdef CONFIG_SYS_INIT_CHAN2 (void) NS16550_init (1, clock_divisor); #endif return (0); }
static int evb64260_serial_init(void) { int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; #ifdef CONFIG_SYS_INIT_CHAN1 (void)NS16550_init(COM_PORTS[0], clock_divisor); #endif #ifdef CONFIG_SYS_INIT_CHAN2 (void)NS16550_init(COM_PORTS[1], clock_divisor); #endif return (0); }
int serial_init (void) { int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; #ifdef CFG_INIT_CHAN1 (void) NS16550_init (COM_PORTS[0], clock_divisor); #endif #ifdef CFG_INIT_CHAN2 (void) NS16550_init (COM_PORTS[1], clock_divisor); #endif return 0; }
int serial_init (void) { DECLARE_GLOBAL_DATA_PTR; int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; #ifdef CFG_INIT_CHAN1 (void)NS16550_init(COM_PORTS[0], clock_divisor); #endif #ifdef CFG_INIT_CHAN2 (void)NS16550_init(COM_PORTS[1], clock_divisor); #endif return (0); }
void board_init_f(ulong bootflag) { int px_spd; u32 plat_ratio, bus_clk, sys_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) /* for FPGA */ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); #else #error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined #endif /* initialize selected port with appropriate baud rate */ px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; bus_clk = sys_clk * plat_ratio / 2; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, CONFIG_SYS_NAND_U_BOOT_RELOC); }
void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; console_init_f(); /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); #ifdef CONFIG_TARGET_P1010RDB_PB setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); #endif /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts("\nSD boot...\n"); #elif defined(CONFIG_SPL_SPI_BOOT) puts("\nSPI Flash boot...\n"); #endif /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); }
void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); #endif /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot...\n"); /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); }
void board_init_f(ulong bootflag) { u32 plat_ratio, ddr_ratio; unsigned long bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); /* Initialize the DDR3 */ sdram_init(); /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, CONFIG_SYS_NAND_U_BOOT_RELOC); }
void dload_serial_init(void) { int clock_divisor; clock_divisor = calc_divisor(serial_ports[0]); NS16550_init(serial_ports[0], clock_divisor); }
void board_init_f(ulong bootflag) { uint plat_ratio, bus_clk, sys_clk = 0; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); uint val, sysclk_mask; val = pgpio->gpdat; sysclk_mask = val & SYSCLK_MASK; if(sysclk_mask == 0) sys_clk = SYSCLK_66; else sys_clk = SYSCLK_100; plat_ratio = gur->porpllsr & 0x0000003e; plat_ratio >>= 1; bus_clk = plat_ratio * sys_clk; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); #ifdef CONFIG_SYS_FSL_BOOT_DDR /* board specific DDR initialization */ initsdram(); #endif /* copy code to DDR and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, CONFIG_SYS_NAND_U_BOOT_RELOC); }
int ns16550_serial_probe(struct udevice *dev) { struct NS16550 *const com_port = dev_get_priv(dev); NS16550_init(com_port, -1); return 0; }
void serial_setbrg (void) { DECLARE_GLOBAL_DATA_PTR; uint32 clock_divisor = 115200 / gd->baudrate; NS16550_init (Com0, clock_divisor); }
int serial_init (void) { int clock_divisor = gd->bus_clk / 16 / gd->baudrate; NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor); return (0); }
int serial_init (void) { // int clock_divisor; // clock_divisor = calc_divisor(serial_ports[0]); NS16550_init(serial_ports[0], 0);//clock_divisor); return (0); }
int serial_init (void) { int clock_divisor = calc_divisor(); NS16550_init(console, clock_divisor); return (0); }
void panic_puts(const char *str) { NS16550_t port = (NS16550_t)0x3f8; NS16550_init(port, 1); while (*str) NS16550_putc(port, *str++); }
int serial_init (void) { int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; (void) NS16550_init (COM_PORTS[0], clock_divisor); gComPort = 0; return 0; }
void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); #elif defined(CONFIG_P1021RDB) par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); #endif /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); #ifndef CONFIG_QE /* init DDR3 reset signal */ puts("\nDDR & BCM56445 reset... "); __raw_writel(0x02210000, &pgpio->gpdir); __raw_writel(0x00210000, &pgpio->gpodr); __raw_writel(0x00000000, &pgpio->gpdat); udelay(20000); __raw_writel(0x00210000, &pgpio->gpdat); udelay(20000); __raw_writel(0x00000000, &pgpio->gpdir); #elif defined(CONFIG_P1021RDB) /* init DDR3 reset signal CE_PB8 */ out_be32(&par_io[1].cpdir1, 0x00004000); out_be32(&par_io[1].cpodr, 0x00800000); out_be32(&par_io[1].cppar1, 0x00000000); /* reset DDR3 */ out_be32(&par_io[1].cpdat, 0x00800000); udelay(1000); out_be32(&par_io[1].cpdat, 0x00000000); udelay(1000); out_be32(&par_io[1].cpdat, 0x00800000); /* disable the CE_PB8 */ out_be32(&par_io[1].cpdir1, 0x00000000); #endif //sdram_reset(); /* Initialize the DDR3 */ sdram_init(); puts("\nsdram_init ok... "); /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, CONFIG_SYS_NAND_U_BOOT_RELOC); }
void _serial_reinit(const int port, int baud_divisor) { #if 1 extern void bc_NS16550_init (NS16550_t com_port, int baud_divisor); bc_NS16550_init(PORT, baud_divisor); #else NS16550_init(PORT, baud_divisor); #endif }
int serial_init (void) { uint32 clock_divisor = 115200 / gd->baudrate; NS16550_init (Com0, clock_divisor); /* NS16550_reinit(Com1, clock_divisor); */ /* serial_puts("COM1: 3F8h initalized"); */ return (0); }
/* * Miscellaneous late-boot configurations * * If a VSC7385 microcode image is present, then upload it. */ int misc_init_r(void) { int rc = 0; #ifdef CONFIG_VSC7385_IMAGE if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, CONFIG_VSC7385_IMAGE_SIZE)) { puts("Failure uploading VSC7385 microcode.\n"); rc = 1; } #endif return rc; } #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif return 0; } #endif #else /* CONFIG_SPL_BUILD */ void board_init_f(ulong bootflag) { board_early_init_f(); NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); puts("NAND boot... "); timer_init(); dram_init(); relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, CONFIG_SYS_NAND_U_BOOT_RELOC); }
int serial_init (void) { DECLARE_GLOBAL_DATA_PTR; int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; (void) NS16550_init (COM_PORTS[0], clock_divisor); gComPort = 0; return 0; }
int serial_init (void) { int clock_divisor; int uart_console; #ifdef CONFIG_NS87308 initialise_ns87308(); #endif #if 0 #ifdef CONFIG_SYS_NS16550_COM1 clock_divisor = calc_divisor(serial_ports[0]); NS16550_init(serial_ports[0], clock_divisor); #endif #ifdef CONFIG_SYS_NS16550_COM2 clock_divisor = calc_divisor(serial_ports[1]); NS16550_init(serial_ports[1], clock_divisor); #endif #ifdef CONFIG_SYS_NS16550_COM3 clock_divisor = calc_divisor(serial_ports[2]); NS16550_init(serial_ports[2], clock_divisor); #endif #ifdef CONFIG_SYS_NS16550_COM4 clock_divisor = calc_divisor(serial_ports[3]); NS16550_init(serial_ports[3], clock_divisor); #endif #else uart_console = uboot_spare_head.boot_data.uart_port; if((uart_console < 0) || (uart_console > 4)) { uart_console = 0; } gpio_request((void *)uboot_spare_head.boot_data.uart_gpio, 2); clock_divisor = calc_divisor(serial_ports[uart_console]); NS16550_init(serial_ports[uart_console], clock_divisor); gd->uart_console = uart_console; #endif return (0); }
int serial_init (void) { int clock_divisor = calc_divisor(); #ifdef CFG_NS87308 initialise_ns87308(); #endif NS16550_init(console, clock_divisor); return (0); }
int serial_init (void) { int clock_divisor = calc_divisor(); #ifdef CFG_NS87308 initialise_ns87308(); #endif NS16550_init(console, clock_divisor); printf("**** Woo hoo! Serial NS16550 is initialized\n"); return (0); }
extern int serial_init (void) { int clock_divisor; #ifdef CFG_NS16550_COM1 clock_divisor = calc_divisor(serial_ports[0]); NS16550_init(serial_ports[0], clock_divisor); #endif #ifdef CFG_NS16550_COM2 clock_divisor = calc_divisor(serial_ports[1]); NS16550_init(serial_ports[1], clock_divisor); #endif #ifdef CFG_NS16550_COM3 clock_divisor = calc_divisor(serial_ports[2]); NS16550_init(serial_ports[2], clock_divisor); #endif #ifdef CFG_NS16550_COM4 clock_divisor = calc_divisor(serial_ports[3]); NS16550_init(serial_ports[3], clock_divisor); #endif return 0; }
int quad_init_dev(unsigned long base) { /* The Quad UART is on the debug board. Check if the debug board is attached before using the UART */ if (zoom2_debug_board_connected()) { NS16550_t port = (NS16550_t) base; int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE; NS16550_init(port, clock_divisor); } /* We have to lie here, otherwise the board init code will hang on the check */ return 0; }
int serial_init (void) { int clock_divisor; #ifdef CONFIG_NS87308 initialise_ns87308(); #endif #if 0 #ifdef CONFIG_SYS_NS16550_COM1 clock_divisor = calc_divisor(serial_ports[0]); NS16550_init(serial_ports[0], clock_divisor); #endif #ifdef CONFIG_SYS_NS16550_COM2 clock_divisor = calc_divisor(serial_ports[1]); NS16550_init(serial_ports[1], clock_divisor); #endif #ifdef CONFIG_SYS_NS16550_COM3 clock_divisor = calc_divisor(serial_ports[2]); NS16550_init(serial_ports[2], clock_divisor); #endif #ifdef CONFIG_SYS_NS16550_COM4 clock_divisor = calc_divisor(serial_ports[3]); NS16550_init(serial_ports[3], clock_divisor); #endif #else if(script_parser_fetch("uart_para", "uart_debug_port", &uart_console, sizeof(int))) uart_console = 0; if((uart_console < 0) || (uart_console > 4)){ uart_console = 0; } clock_divisor = calc_divisor(serial_ports[uart_console]); NS16550_init(serial_ports[uart_console], clock_divisor); #endif return (0); }
int serial_init (void) { int clock_divisor = calc_divisor(); #ifdef CFG_NS87308 initialise_ns87308(); #endif NS16550_init(console, clock_divisor); #if (CONFIG_CONS_INDEX == 1) if (omap_revision() == OMAP4470_ES1_0) set_uart1_gpios(); #endif return (0); }