int trigger_isr_start(void (*func)(void)) {
/* Check callback and set */
if (func == NULL) {
return -1;
}
callback = func;
/* Clear Pending ISR */
NVIC_ICPR(TRIGGER_ISR_BITREG) |= 1 << (TRIGGER_ISR_IRQ%32);
/* Enable ISR */
NVIC_ISER(TRIGGER_ISR_BITREG) |= 1 << (TRIGGER_ISR_IRQ%32);
/* NVIC_IP is 8 bits wide, upper half contains priority so we shift
* up by 4. The actual register is 32 bits, but the headers only expose 8.
* This is easier than doing the other bit messing.
*/
NVIC_IP(TRIGGER_ISR_IRQ) = (TRIGGER_ISR_PRI) << 4;
/* Set port to GPIO- Needed for interrupt for some reason */
TRIGGER_PCR &= ~PORT_PCR_MUX_MASK;
TRIGGER_PCR |= PORT_PCR_MUX(1);
/* Clear interrupt flag */
TRIGGER_PCR |= PORT_PCR_ISF_MASK;
/* Set interrupt to correct edge & enable */
TRIGGER_PCR &= ~PORT_PCR_IRQC_MASK;
TRIGGER_PCR |= ((TRIGGER_EDGE) ? (0b1001) : (0b1010)) << PORT_PCR_IRQC_SHIFT;
/* Success */
return 0;
}
void trigger_isr_stop(void) {
/* Unset interrupt */
TRIGGER_PCR &= ~PORT_PCR_IRQC_MASK;
/* Clear interrupt flag */
TRIGGER_PCR |= PORT_PCR_ISF_MASK;
/* Set port mux to 0 (disabled) */
TRIGGER_PCR &= ~PORT_PCR_MUX_MASK;
/* Clear Pending ISR */
NVIC_ICPR(TRIGGER_ISR_BITREG) |= 1 << (TRIGGER_ISR_IRQ%32);
}
/*
* Check active state
* Current active state for the associated interrupt
*/
EXPORT BOOL CheckInt( INTVEC intvec )
{
return (*(_UW*)(NVIC_ICPR(intvec)) & (0x01U << (intvec % 32)));
}
/*
* Clear-Pending
* Un-pends the associated interrupt under software control.
*/
EXPORT void ClearPendingInt( INTVEC intvec )
{
*(_UW*)(NVIC_ICPR(intvec)) = (0x01U << (intvec % 32));
}
static void
chx_clr_intr (uint8_t irq_num)
{ /* Clear pending interrupt. */
NVIC_ICPR (irq_num) = 1 << (irq_num & 0x1f);
}
void nvic_clear_pending_irq(uint8_t irqn)
{
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
}
