/* ===================================================================*/ LDD_TDeviceData* ExtIntLdd5_Init(LDD_TUserData *UserDataPtr) { /* Allocate LDD device structure */ ExtIntLdd5_TDeviceData *DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Store the UserData pointer */ DeviceDataPrv->UserData = UserDataPtr; /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_PORTE__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* Initialization of Port Control registers */ /* PORTE_PCR11: ISF=0,MUX=1 */ PORTE_PCR11 = (uint32_t)((PORTE_PCR11 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x06) )) | (uint32_t)( PORT_PCR_MUX(0x01) )); /* PORTE_PCR11: ISF=1,IRQC=9 */ PORTE_PCR11 = (uint32_t)((PORTE_PCR11 & (uint32_t)~(uint32_t)( PORT_PCR_IRQC(0x06) )) | (uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_IRQC(0x09) )); /* NVICIP91: PRI91=0x80 */ NVICIP91 = NVIC_IP_PRI91(0x80); /* NVICISER2: SETENA|=0x08000000 */ NVICISER2 |= NVIC_ISER_SETENA(0x08000000); /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ExtIntLdd5_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
/* ===================================================================*/ LDD_TDeviceData* I2C2_Init(LDD_TUserData *UserDataPtr) { /* Allocate HAL device structure */ I2C2_TDeviceData *DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vector */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_I2C0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; DeviceDataPrv->SerFlag = 0x00U; /* Reset all flags */ DeviceDataPrv->SendStop = LDD_I2C_SEND_STOP; /* Set variable for sending stop condition (for master mode) */ DeviceDataPrv->InpLenM = 0x00U; /* Set zero counter of data of reception */ DeviceDataPrv->OutLenM = 0x00U; /* Set zero counter of data of transmission */ /* SIM_SCGC4: I2C0=1 */ SIM_SCGC4 |= SIM_SCGC4_I2C0_MASK; /* I2C0_C1: IICEN=0,IICIE=0,MST=0,TX=0,TXAK=0,RSTA=0,WUEN=0,DMAEN=0 */ I2C0_C1 = 0x00U; /* Clear control register */ /* I2C0_FLT: SHEN=0,STOPF=1,STOPIE=0,FLT=0 */ I2C0_FLT = (I2C_FLT_STOPF_MASK | I2C_FLT_FLT(0x00)); /* Clear bus status interrupt flags */ /* I2C0_S: TCF=0,IAAS=0,BUSY=0,ARBL=0,RAM=0,SRW=0,IICIF=1,RXAK=0 */ I2C0_S = I2C_S_IICIF_MASK; /* Clear interrupt flag */ /* PORTE_PCR25: ISF=0,MUX=5 */ PORTE_PCR25 = (uint32_t)((PORTE_PCR25 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x02) )) | (uint32_t)( PORT_PCR_MUX(0x05) )); /* PORTE_PCR24: ISF=0,MUX=5 */ PORTE_PCR24 = (uint32_t)((PORTE_PCR24 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x02) )) | (uint32_t)( PORT_PCR_MUX(0x05) )); /* NVIC_IPR2: PRI_8=0x80 */ NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_8(0x7F) )) | (uint32_t)( NVIC_IP_PRI_8(0x80) )); /* NVIC_ISER: SETENA|=0x0100 */ NVIC_ISER |= NVIC_ISER_SETENA(0x0100); /* I2C0_C2: GCAEN=0,ADEXT=0,HDRS=0,SBRC=0,RMEN=0,AD=0 */ I2C0_C2 = I2C_C2_AD(0x00); /* I2C0_FLT: SHEN=0,STOPF=0,STOPIE=0,FLT=0 */ I2C0_FLT = I2C_FLT_FLT(0x00); /* Set glitch filter register */ /* I2C0_SMB: FACK=0,ALERTEN=0,SIICAEN=0,TCKSEL=0,SLTF=1,SHTF1=0,SHTF2=0,SHTF2IE=0 */ I2C0_SMB = I2C_SMB_SLTF_MASK; /* I2C0_F: MULT=0,ICR=0 */ I2C0_F = (I2C_F_MULT(0x00) | I2C_F_ICR(0x00)); /* Set prescaler bits */ I2C_PDD_EnableDevice(I2C0_BASE_PTR, PDD_ENABLE); /* Enable device */ I2C_PDD_EnableInterrupt(I2C0_BASE_PTR); /* Enable interrupt */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_I2C2_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */ }
void UART_init(void) { // Habilito la llave general de las interrupciones NVICISER0 |= NVIC_ISER_SETENA(1<<31); //Habilito los cuatro modulos de UART SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; // Habilito el pin PTC1 como salida del canal 0 PORTB_PCR16 = (PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03)); //Tx PORTB_PCR17 = (PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03)); //Rx //Habilito por interrupcion, un bit de stop y baudrate UART_C1_REG(UART0_BASE_PTR) = 0x00; UART_BDH_REG(UART0_BASE_PTR) = /*UART_BDH_RXEDGIE_MASK | */UART_BDH_SBR(BAUDRATEHIGH); UART_BDL_REG(UART0_BASE_PTR) = UART_BDL_SBR(BAUDRATELOW); UART_C2_REG(UART0_BASE_PTR) = UART_C2_TIE_MASK | UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK; UART_C3_REG(UART0_BASE_PTR) = UART_C3_TXDIR_MASK; UART_PFIFO_REG(UART0_BASE_PTR) = UART_PFIFO_TXFE_MASK | UART_PFIFO_TXFIFOSIZE(0x06) | UART_PFIFO_RXFE_MASK | UART_PFIFO_RXFIFOSIZE(0x01); UART_S2_REG(UART0_BASE_PTR) = 0x00; }
/* ===================================================================*/ LDD_TDeviceData* FTM_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ FTM_TDeviceData *DeviceDataPrv; /* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Interrupt vector(s) allocation */ /* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */ /* Note: Exception handler for interrupt is not saved, because it is not modified */ DeviceDataPrv->SavedISRSettings_TUInterrupt.isrData = _int_get_isr_data(LDD_ivIndex_INT_LPTimer); DeviceDataPrv->SavedISRSettings_TUInterrupt.isrFunction = _int_install_isr(LDD_ivIndex_INT_LPTimer, FTM_Interrupt, DeviceDataPrv); /* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=1,TIE=0,TPS=0,TPP=0,TFC=0,TMS=0,TEN=0 */ LPTMR0_CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00)); /* Clear control register */ /* LPTMR0_CMR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COMPARE=0x1387 */ LPTMR0_CMR = LPTMR_CMR_COMPARE(0x1387); /* Set up compare register */ /* LPTMR0_PSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PRESCALE=1,PBYP=0,PCS=0 */ LPTMR0_PSR = (LPTMR_PSR_PRESCALE(0x01) | LPTMR_PSR_PCS(0x00)); /* Set up prescaler register */ /* NVICIP58: PRI58=0x70 */ NVICIP58 = NVIC_IP_PRI58(0x70); /* NVICISER1: SETENA|=0x04000000 */ NVICISER1 |= NVIC_ISER_SETENA(0x04000000); /* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=0,TIE=1,TPS=0,TPP=0,TFC=0,TMS=0,TEN=1 */ LPTMR0_CSR = (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TPS(0x00) | LPTMR_CSR_TEN_MASK); /* Set up control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_FTM_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
BOOL RTC_Init() { //enable the clock gate to the RTC module SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; //configure the required load capacitance (18pf) RTC_CR |= (RTC_CR_SC2P_MASK | RTC_CR_SC16P_MASK); //enable the 32.768 KHZ crystal oscillator RTC_CR |= RTC_CR_OSCE_MASK; //lock the control register RTC_LR |= RTC_LR_CRL_MASK; //enable the time counter and set the time second register start from 0 RTC_SR |= RTC_SR_TCE_MASK; // RTC_TSR = 0; //enable the time second interrupt RTC_IER |= RTC_IER_TSIE_MASK; // initialize NVIC // Vector 0x53, IRQ = 67, location = IRQ mod 32 = 3 // NVIC non-IPR=2 IPR=16 // clear pending interrupts NVICICPR2 = NVIC_ICPR_CLRPEND(1 << 3); //Enable interrupts NVICISER2 = NVIC_ISER_SETENA(1 << 3); RTCCallbackSemaphore = OS_SemaphoreCreate(0); return bTRUE; }
void i2c_init (void) { /* * this function initializes the I2C bus to use interrupts */ if (i2c_initialize == TRUE) { return; // already initialized } memset(&i2c_buf, 0x00, sizeof(i2c_buf)); /* SIM_SCGC4: I2C0=1 */ SIM_SCGC4 |= SIM_SCGC4_I2C0_MASK; /* I2C0_C1: IICEN=0,IICIE=0,MST=0,TX=0,TXAK=0,RSTA=0,WUEN=0,DMAEN=0 */ I2C0_C1 = 0x00U; /* Clear control register */ /* I2C0_FLT: SHEN=0,STOPF=1,STOPIE=0,FLT=0 */ I2C0_FLT = I2C_FLT_STOPF_MASK; /* Clear bus status interrupt flags */ /* I2C0_S: TCF=0,IAAS=0,BUSY=0,ARBL=0,RAM=0,SRW=0,IICIF=1,RXAK=0 */ I2C0_S = I2C_S_IICIF_MASK; /* Clear interrupt flag */ /* PORTB_PCR1: ISF=0,MUX=2 */ PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* PORTB_PCR0: ISF=0,MUX=2 */ PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* NVIC_IPR2: PRI_8=0x80 */ NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_8(0x7F) )) | (uint32_t)( NVIC_IP_PRI_8(0x80) )); /* NVIC_ISER: SETENA|=0x0100 */ NVIC_ISER |= NVIC_ISER_SETENA(0x0100); /* I2C0_C2: GCAEN=0,ADEXT=0,HDRS=0,SBRC=0,RMEN=0,AD=0 */ I2C0_C2 = 0x00U; /* I2C0_FLT: SHEN=0,STOPF=0,STOPIE=0,FLT=0 */ I2C0_FLT = 0x00U; /* Set glitch filter register */ /* I2C0_SMB: FACK=0,ALERTEN=0,SIICAEN=0,TCKSEL=0,SLTF=1,SHTF1=0,SHTF2=0,SHTF2IE=0 */ I2C0_SMB = I2C_SMB_SLTF_MASK; /* I2C0_F: MULT=0,ICR=2 */ //I2C0_F = I2C_F_ICR(0x02); /* Set prescaler bits */ /* I2C0_F: MULT=0,ICR=F = /68 p.706 of http://cache.freescale.com/files/32bit/doc/ref_manual/KL25P80M48SF0RM.pdf */ I2C0_F = I2C_F_ICR(0x02); //I2C_F_ICR(0x0F); /* Set prescaler bits */ //I2C_PDD_EnableDevice(I2C0_BASE_PTR, PDD_ENABLE); /* Enable device */ #define PDD_ENABLE 1u /* Enable I2C device */ I2C_C1_REG(I2C0_BASE_PTR) = (uint_8) ((I2C_C1_REG(I2C0_BASE_PTR) & ~I2C_C1_IICEN_MASK | 1u << I2C_C1_IICEN_SHIFT)); // TODO: fix this, I am pretty sure |= will work //I2C_PDD_EnableInterrupt(I2C0_BASE_PTR); /* Enable interrupt */ I2C_C1_REG(I2C0_BASE_PTR) |= I2C_C1_IICIE_MASK; i2c_initialize = TRUE; }
/* ===================================================================*/ LDD_TDeviceData* AS1_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ AS1_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vectors */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_UART1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC4: UART1=1 */ SIM_SCGC4 |= SIM_SCGC4_UART1_MASK; /* PORTE_PCR1: ISF=0,MUX=3 */ PORTE_PCR1 = (uint32_t)((PORTE_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); /* PORTE_PCR0: ISF=0,MUX=3 */ PORTE_PCR0 = (uint32_t)((PORTE_PCR0 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); /* NVIC_IPR3: PRI_13=0x80 */ NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_13(0x7F) )) | (uint32_t)( NVIC_IP_PRI_13(0x80) )); /* NVIC_ISER: SETENA|=0x2000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x2000); UART_PDD_EnableTransmitter(UART1_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART_PDD_EnableReceiver(UART1_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ /* UART1_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ UART1_C1 = 0x00U; /* Set the C1 register */ /* UART1_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */ UART1_C3 = 0x00U; /* Set the C3 register */ /* UART1_S2: LBKDIF=0,RXEDGIF=0,??=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */ UART1_S2 = 0x00U; /* Set the S2 register */ UART_PDD_SetBaudRate(UART1_BASE_PTR, 137U); /* Set the baud rate register. */ UART_PDD_EnableTransmitter(UART1_BASE_PTR, PDD_ENABLE); /* Enable transmitter */ UART_PDD_EnableReceiver(UART1_BASE_PTR, PDD_ENABLE); /* Enable receiver */ UART_PDD_EnableInterrupt(UART1_BASE_PTR, ( UART_PDD_INTERRUPT_RECEIVER )); /* Enable interrupts */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_AS1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
/* ===================================================================*/ LDD_TDeviceData* UART_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ UART_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vectors */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_UART0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC4: UART0=1 */ SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /* PORTA_PCR1: ISF=0,MUX=2 */ PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* PORTA_PCR2: ISF=0,MUX=2 */ PORTA_PCR2 = (uint32_t)((PORTA_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* NVIC_IPR3: PRI_12=0x80 */ NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_12(0x7F) )) | (uint32_t)( NVIC_IP_PRI_12(0x80) )); /* NVIC_ISER: SETENA|=0x1000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x1000); UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ /* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ UART0_C1 = 0x00U; /* Set the C1 register */ /* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */ UART0_C3 = 0x00U; /* Set the C3 register */ /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */ UART0_C4 = UART0_C4_OSR(0x00); /* Set the C4 register */ /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */ UART0_S2 = 0x00U; /* Set the S2 register */ UART_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Initial speed CPU mode is high */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_UART_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
/* ===================================================================*/ LDD_TDeviceData* CI2C1_Init(LDD_TUserData *UserDataPtr) { /* Allocate HAL device structure */ CI2C1_TDeviceData *DeviceDataPrv; /* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vector */ /* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */ /* Note: Exception handler for interrupt is not saved, because it is not modified */ DeviceDataPrv->SavedISRSettings.isrData = _int_get_isr_data(LDD_ivIndex_INT_I2C0); DeviceDataPrv->SavedISRSettings.isrFunction = _int_install_isr(LDD_ivIndex_INT_I2C0, CI2C1_Interrupt, DeviceDataPrv); DeviceDataPrv->SerFlag = 0x00U; /* Reset all flags */ DeviceDataPrv->SendStop = LDD_I2C_SEND_STOP; /* Set variable for sending stop condition (for master mode) */ DeviceDataPrv->InpLenM = 0x00U; /* Set zero counter of data of reception */ DeviceDataPrv->OutLenM = 0x00U; /* Set zero counter of data of transmission */ /* SIM_SCGC4: I2C0=1 */ SIM_SCGC4 |= SIM_SCGC4_I2C0_MASK; /* I2C0_C1: IICEN=0,IICIE=0,MST=0,TX=0,TXAK=0,RSTA=0,WUEN=0,DMAEN=0 */ I2C0_C1 = 0x00U; /* Clear control register */ /* I2C0_S: TCF=0,IAAS=0,BUSY=0,ARBL=0,RAM=0,SRW=0,IICIF=1,RXAK=0 */ I2C0_S = I2C_S_IICIF_MASK; /* Clear interrupt flag */ /* PORTB_PCR1: ISF=0,MUX=2 */ PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); PORT_PDD_SetPinOpenDrain(PORTB_BASE_PTR, 0x01u, PORT_PDD_OPEN_DRAIN_ENABLE); /* Set SDA pin as open drain */ /* PORTB_PCR0: ISF=0,MUX=2 */ PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); PORT_PDD_SetPinOpenDrain(PORTB_BASE_PTR, 0x00u, PORT_PDD_OPEN_DRAIN_ENABLE); /* Set SCL pin as open drain */ /* NVICIP24: PRI24=0x80 */ NVICIP24 = NVIC_IP_PRI24(0x80); /* NVICISER0: SETENA|=0x01000000 */ NVICISER0 |= NVIC_ISER_SETENA(0x01000000); /* I2C0_C2: GCAEN=0,ADEXT=0,HDRS=0,SBRC=0,RMEN=0,AD=0 */ I2C0_C2 = I2C_C2_AD(0x00); /* I2C0_FLT: ??=0,??=0,??=0,FLT=0 */ I2C0_FLT = I2C_FLT_FLT(0x00); /* Set glitch filter register */ /* I2C0_SMB: FACK=0,ALERTEN=0,SIICAEN=0,TCKSEL=0,SLTF=1,SHTF1=0,SHTF2=0,SHTF2IE=0 */ I2C0_SMB = I2C_SMB_SLTF_MASK; /* I2C0_F: MULT=1,ICR=0x17 */ I2C0_F = (I2C_F_MULT(0x01) | I2C_F_ICR(0x17)); /* Set prescaler bits */ I2C_PDD_EnableDevice(I2C0_BASE_PTR, PDD_ENABLE); /* Enable device */ I2C_PDD_EnableInterrupt(I2C0_BASE_PTR); /* Enable interrupt */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_CI2C1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */ }
BOOL Accel_Init(const TAccelSetup* const accelSetup) { TAccelMode CurrentMode; DataCallback = accelSetup->dataReadyCallbackFunction; DataCallbackArgument = accelSetup->dataReadyCallbackArguments; ReadCallback = accelSetup->readCompleteCallbackFunction; ReadCallbackArgument = accelSetup->readCompleteCallbackArguments; //Let there be clocks! SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; /*portb GPIO, clear interrupt, interrupt on falling edge.*/ PORTB_PCR7 = (PORT_PCR_MUX(0x01) | PORT_PCR_ISF_MASK | PORT_PCR_IRQC(0x0A)); /* NVICIP88: PRI88=0x80 */ NVICIP88 = NVIC_IP_PRI88(0x80); /* NVICISER2: SETENA|=0x01000000 */ NVICISER2 |= NVIC_ISER_SETENA(0x01000000); //Check if we are connected to the correct device uint8_t whoAmI; I2C_SelectSlaveDevice(MMA8451Q_ADDR_SA0_HIGH); //TODO: uncomment /* I2C_PollRead(MMA8451Q_WHO_AM_I, &whoAmI, 1); if (whoAmI != MMA8451Q_WHO_AM_I_VALUE) { //This is not the i2c device we are looking for return bFALSE; } */ //Reset the accelerometer //TODO: uncomment /*I2C_Write(MMA8451Q_CTRL_REG2, MMA8451Q_CTRL_REG2_RST_MASK, bFALSE); uint8_t reg2 = MMA8451Q_CTRL_REG2_RST_MASK; while (reg2 & MMA8451Q_CTRL_REG2_RST_MASK) { I2C_PollRead(MMA8451Q_CTRL_REG2, ®2, 1); }*/ /* * activate * enable fast read * low noise * data rate 1.56Hz (0x38) * */ I2C_Write(MMA8451Q_CTRL_REG1, (0x38 | MMA8451Q_CTRL_REG1_ACTIVE_MASK | MMA8451Q_CTRL_REG1_F_READ_MASK | MMA8451Q_CTRL_REG1_LNOISE_MASK), bFALSE); return bTRUE; }
/* ===================================================================*/ LDD_TDeviceData* DMA1_Init(LDD_TUserData *UserDataPtr) { uint8_t i; DMA1_TDeviceData *DeviceDataPtr; /* LDD device structure */ DMA1_TDescriptorRecord *DescriptorRecordPtr; /* Auxiliary local pointer to internal descriptor records. */ /* Allocate HAL device structure */ /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPtr = &DeviceDataPtr__DEFAULT_RTOS_ALLOC; DeviceDataPtr->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Enable device clock gate */ /* SIM_SCGC7: DMA=1 */ SIM_SCGC7 |= SIM_SCGC7_DMA_MASK; /* SIM_SCGC6: DMAMUX=1 */ SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK; /* Transfer compete interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_DMA2__DEFAULT_RTOS_ISRPARAM = DeviceDataPtr; /* Transfer compete interrupt vector(s) priority setting */ /* NVIC_IPR0: PRI_2=0x80 */ NVIC_IPR0 = (uint32_t)((NVIC_IPR0 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_2(0x7F) )) | (uint32_t)( NVIC_IP_PRI_2(0x80) )); /* NVIC_ISER: SETENA|=4 */ NVIC_ISER |= NVIC_ISER_SETENA(0x04); for (i = 0U; i < DMA1_DMA_CHANNELS_NUMBER; i++) { DMA_PDD_WriteControlReg(DMA_BASE_PTR, i, 0U); /* Clear control register. Disable all interrupts and HW requests. */ DMA_PDD_ClearInterruptFlags(DMA_BASE_PTR, i, DMA_PDD_TRANSFER_COMPLETE_FLAG); /* Clear request interrupt flags */ } /* Initialization of channels record field. */ memset(DeviceDataPtr->ChannelRecord, 0, DMA1_DMA_CHANNELS_NUMBER * sizeof(DeviceDataPtr->ChannelRecord[0])); //for(i = 0U; i < DMA1_DMA_CHANNELS_NUMBER; i++) { // DeviceDataPtr->ChannelRecord[i] = NULL; /* Clear pointer to descriptor record of all channels. */ //} /* Initialization of channel and descriptor record fields. */ for(i = 0U; i < DMA1_CONFIGURED_CHANNELS_NUMBER; i++) { DescriptorRecordPtr = &(DeviceDataPtr->DescriptorRecord[i]); /* Store local pointer to descriptor record. */ DescriptorRecordPtr->ChannelNumber = DMA1_ChannelNumbers[i]; /* Store associated channel number. */ DescriptorRecordPtr->DescriptorPtr = NULL; /* Set channel as free. */ DescriptorRecordPtr->Interrupts = DMA1_ChannelInterrupts[i]; /* Store associated channel interrupts enabled/disabled status. */ DescriptorRecordPtr->Initialized = FALSE; /* Set channel as not initialized. */ DescriptorRecordPtr->Enabled = FALSE; /* Set channel as disabled. */ DeviceDataPtr->ChannelRecord[DMA1_ChannelNumbers[i]] = DescriptorRecordPtr; /* Store pointers to descriptor records of fixed channels. */ DeviceDataPtr->EventMask[DMA1_ChannelNumbers[i]] = 0U; /* Clear channel event mask. */ } /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_DMA1_ID,DeviceDataPtr); return ((LDD_TDeviceData *)DeviceDataPtr); /* Return pointer to the data structure */ }
/*-----------------------------------------------------------*/ void vPortInitTickTimer(void) { #if configUSE_TICKLESS_IDLE == 1 { #if TICK_NOF_BITS==32 xMaximumPossibleSuppressedTicks = 0xffffffffUL/TIMER_COUNTS_FOR_ONE_TICK; /* 32bit timer register */ #elif TICK_NOF_BITS==24 xMaximumPossibleSuppressedTicks = 0xffffffUL/TIMER_COUNTS_FOR_ONE_TICK; /* 24bit timer register */ #elif TICK_NOF_BITS==16 xMaximumPossibleSuppressedTicks = 0xffffUL/TIMER_COUNTS_FOR_ONE_TICK; /* 16bit timer register */ #elif TICK_NOF_BITS==8 xMaximumPossibleSuppressedTicks = 0xffUL/TIMER_COUNTS_FOR_ONE_TICK; /* 8bit timer register */ #else error "unknown configuration!" #endif #if configSYSTICK_USE_LOW_POWER_TIMER ulStoppedTimerCompensation = configSTOPPED_TIMER_COMPENSATION/(configCPU_CLOCK_HZ/configSYSTICK_LOW_POWER_TIMER_CLOCK_HZ); #else ulStoppedTimerCompensation = configSTOPPED_TIMER_COMPENSATION/(configCPU_CLOCK_HZ/configSYSTICK_CLOCK_HZ); #endif } #endif /* configUSE_TICKLESS_IDLE */ #if configSYSTICK_USE_LOW_POWER_TIMER SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* enable clock: SIM_SCGC5: LPTMR=1 */ /* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=1,TIE=0,TPS=0,TPP=0,TFC=0,TMS=0,TEN=0 */ LPTMR0_CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00)); /* Clear control register */ /* LPTMR0_PSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PRESCALE=0,PBYP=1,PCS=1 */ LPTMR0_PSR = LPTMR_PSR_PRESCALE(0x00) | /* prescaler value */ LPTMR_PSR_PBYP_MASK | /* prescaler bypass */ LPTMR_PSR_PCS(0x01); /* Clock source */ /* * PBYP PCS * ERCLK32 1 10 * LPO_1kHz 1 01 * ERCLK 0 00 * IRCLK 1 00 */ *(portNVIC_SYSPRI7) |= portNVIC_LP_TIMER_PRI; /* set priority of low power timer interrupt */ /* NVIC_ISER: SETENA|=0x10000000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x10000000); /* 0xE000E100 <= 0x10000000 */ /* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=0,TIE=0,TPS=0,TPP=0,TFC=0,TMS=0,TEN=1 */ LPTMR0_CSR = (LPTMR_CSR_TPS(0x00) | LPTMR_CSR_TEN_MASK); /* Set up control register */ #else /* use normal SysTick Counter */ *(portNVIC_SYSPRI3) |= portNVIC_SYSTICK_PRI; /* set priority of SysTick interrupt */ #endif /* Configure timer to interrupt at the requested rate. */ SET_TICK_DURATION(TIMER_COUNTS_FOR_ONE_TICK-1UL); RESET_TICK_COUNTER_VAL(); ENABLE_TICK_COUNTER(); }
/* ===================================================================*/ LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr) { TU2_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID] == NULL) { /* Allocate device structure */ /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU2_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_FTM1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC6: FTM1=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK; /* FTM1_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM1_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */ /* FTM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM1_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */ /* FTM1_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM1_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */ /* FTM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM1_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */ /* FTM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM1_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM1_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xFFFF */ FTM1_MOD = FTM_MOD_MOD(0xFFFF); /* Set up modulo register */ DeviceDataPrv->EnEvents = 0x0100U; /* Enable selected events */ /* NVICIP26: PRI26=0x80 */ NVICIP26 = NVIC_IP_PRI26(0x80); /* NVICISER0: SETENA|=0x04000000 */ NVICISER0 |= NVIC_ISER_SETENA(0x04000000); /* FTM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=1,CPWMS=0,CLKS=1,PS=3 */ FTM1_SC = (FTM_SC_TOIE_MASK | FTM_SC_CLKS(0x01) | FTM_SC_PS(0x03)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* ===================================================================*/ LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ TU2_TDeviceData *DeviceDataPrv; /* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Interrupt vector(s) allocation */ /* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_TPM1__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC6: TPM1=1 */ SIM_SCGC6 |= SIM_SCGC6_TPM1_MASK; /* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=0,PS=0 */ TPM1_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x00)); /* Clear status and control register */ /* TPM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ TPM1_CNT = TPM_CNT_COUNT(0x00); /* Reset counter register */ /* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ TPM1_C0SC = 0x00U; /* Clear channel status and control register */ /* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ TPM1_C1SC = 0x00U; /* Clear channel status and control register */ /* TPM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xFFFF */ TPM1_MOD = TPM_MOD_MOD(0xFFFF); /* Set up modulo register */ /* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=1,MSB=0,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ TPM1_C1SC = (TPM_CnSC_CHIE_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* PORTA_PCR13: ISF=0,MUX=3 */ PORTA_PCR13 = (uint32_t)((PORTA_PCR13 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); DeviceDataPrv->EnEvents = 0x0101U; /* Enable selected events */ /* NVIC_IPR4: PRI_18=0x80 */ NVIC_IPR4 = (uint32_t)((NVIC_IPR4 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_18(0x7F) )) | (uint32_t)( NVIC_IP_PRI_18(0x80) )); /* NVIC_ISER: SETENA|=0x00040000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x00040000); /* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=1,CPWMS=0,CMOD=1,PS=4 */ TPM1_SC = (TPM_SC_TOIE_MASK | TPM_SC_CMOD(0x01) | TPM_SC_PS(0x04)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* Directs the Nested Vectored Interrupt Controller (NVIC) to enable interrupts * from the specified device at the specified priority level * * Parameters: * IRQ identifies the device through its interrupt request number (IRQ) * priority the priority level requested * * If either the IRQ number or the priority is invalid, this function performs no * action */ void NVICEnableIRQ(int IRQ, unsigned char priority) { int nonIPRRegisterNumber; int bitWithinNonIPRRegister; if(IRQ < 0 || IRQ > NVIC_MaxIRQ) return; if(priority > NVIC_MaxPriority) return; nonIPRRegisterNumber = IRQ/NVIC_FieldsPerNonIPRRegister; bitWithinNonIPRRegister = IRQ%NVIC_FieldsPerNonIPRRegister; /* The IRQ for a device is its interrupt vector number minus 16. * The first 16 vectors are reserved for ARM core interrupts. */ /* Enable interrupts from the requested IRQ using the appropriate NVIC_ISER * register (Interrupt Set-Enable Registers) (See B3.4.3 on page B3-755 of * the ARM®v7-M Architecture Reference Manual, Errata markup, * ARM DDI 0403Derrata 2010_Q3 (ID100710)) */ NVIC_ISER_REG(NVIC_BASE_PTR, nonIPRRegisterNumber) = NVIC_ISER_SETENA(1<<bitWithinNonIPRRegister); /* Set the interrupt priority of the requested IRQ using the appropriate * NVIC_IPR register (Interrupt Priority Registers) (See B3.4.8 on page B3-760 * of the ARM®v7-M Architecture Reference Manual, Errata markup, * ARM DDI 0403Derrata 2010_Q3 (ID100710)) */ /* The ARMv7-M Architecture Reference Manual in section "B1.5.4 Exception * priorities and preemption" on page B1-635 states, "The number of * supported priority values is an IMPLEMENTATION DEFINED power of two in * the range 8 to 256, and the minimum supported priority value is always 0. * All priority value fields are 8-bits, and if an implementation supports * fewer than 256 priority levels then low-order bits of these fields are RAZ." * * In the K70 Sub-Family Reference Manual in section "3.2.2.1 Interrupt * priority levels" on page 85, it states, "This device supports 16 priority * levels for interrupts. Therefore, in the NVIC each source in the IPR * registers contains 4 bits." The diagram that follows goes on to confirm * that only the high-order 4 bits of each 8 bit field is used. It doesn't * explicitly mention the System Handler (like the SVC handler) priorities, * but they should be handled consistently with the interrupt priorities. */ NVIC_IP_REG(NVIC_BASE_PTR, IRQ) = priority << NVIC_PriorityShift; }
/* ===================================================================*/ LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr) { TU1_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) { /* Allocate device structure */ /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_LPTimer__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC5: LPTMR=1 */ SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=1,TIE=0,TPS=0,TPP=0,TFC=0,TMS=0,TEN=0 */ LPTMR0_CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00)); /* Clear control register */ /* LPTMR0_CMR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COMPARE=0xFFFF */ LPTMR0_CMR = LPTMR_CMR_COMPARE(0xFFFF); /* Set up compare register */ /* LPTMR0_PSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PRESCALE=0,PBYP=1,PCS=0 */ LPTMR0_PSR = LPTMR_PSR_PRESCALE(0x00) | LPTMR_PSR_PBYP_MASK | LPTMR_PSR_PCS(0x00); /* Set up prescaler register */ /* NVIC_IPR7: PRI_28=0x80 */ NVIC_IPR7 = (uint32_t)((NVIC_IPR7 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_28(0x7F) )) | (uint32_t)( NVIC_IP_PRI_28(0x80) )); /* NVIC_ISER: SETENA|=0x10000000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x10000000); /* LPTMR0_CSR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF=0,TIE=1,TPS=0,TPP=0,TFC=0,TMS=0,TEN=1 */ LPTMR0_CSR = (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TPS(0x00) | LPTMR_CSR_TEN_MASK); /* Set up control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* ===================================================================*/ LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr) { TU1_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) { /* Allocate device structure */ /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_PIT__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC6: PIT=1 */ SIM_SCGC6 |= SIM_SCGC6_PIT_MASK; /* PIT_MCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MDIS=0,FRZ=0 */ PIT_MCR = 0x00U; /* Enable device clock */ /* PIT_TCTRL0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHN=0,TIE=0,TEN=0 */ PIT_TCTRL0 = 0x00U; /* Clear control register */ /* PIT_TFLG0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TIF=1 */ PIT_TFLG0 = PIT_TFLG_TIF_MASK; /* Clear timer flag register */ /* PIT_LDVAL0: TSV=0x4E1F */ PIT_LDVAL0 = PIT_LDVAL_TSV(0x4E1F); /* Set up load register */ /* NVIC_IPR5: PRI_22=0x80 */ NVIC_IPR5 = (uint32_t)((NVIC_IPR5 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_22(0x7F) )) | (uint32_t)( NVIC_IP_PRI_22(0x80) )); /* NVIC_ISER: SETENA|=0x00400000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x00400000); /* PIT_TCTRL0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHN=0,TIE=1,TEN=1 */ PIT_TCTRL0 = (PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK); /* Set up control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* ===================================================================*/ LDD_TDeviceData* ExtIntLdd1_Init(LDD_TUserData *UserDataPtr) { /* Allocate LDD device structure */ ExtIntLdd1_TDeviceData *DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Store the UserData pointer */ DeviceDataPrv->UserData = UserDataPtr; /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_PORTC__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* Enable device clock gate */ /* SIM_SCGC5: PORTC=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK; /* Initialization of pin routing */ /* PORTC_PCR7: ISF=0,MUX=1 */ PORTC_PCR7 = (uint32_t)((PORTC_PCR7 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x06) )) | (uint32_t)( PORT_PCR_MUX(0x01) )); /* PORTC_PCR7: ISF=1,IRQC=9 */ PORTC_PCR7 = (uint32_t)((PORTC_PCR7 & (uint32_t)~(uint32_t)( PORT_PCR_IRQC(0x06) )) | (uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_IRQC(0x09) )); /* NVICIP61: PRI61=0x70 */ NVICIP61 = NVIC_IP_PRI61(0x70); /* NVICISER1: SETENA|=0x20000000 */ NVICISER1 |= NVIC_ISER_SETENA(0x20000000); /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ExtIntLdd1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
/* ** =================================================================== ** Method : ExtIntLdd7_Init (component ExtInt_LDD) ** ** Description : ** This method initializes the associated peripheral(s) and the ** component internal variables. The method is called ** automatically as a part of the application initialization ** code. ** Parameters : ** NAME - DESCRIPTION ** * UserDataPtr - Pointer to the RTOS device ** structure. This pointer will be passed to ** all events as parameter. ** Returns : ** --- - Pointer to the dynamically allocated ** private structure or NULL if there was an ** error. ** =================================================================== */ LDD_TDeviceData* ExtIntLdd7_Init(LDD_TUserData *UserDataPtr) { /* Allocate LDD device structure */ ExtIntLdd7_TDeviceData *DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Store the UserData pointer */ DeviceDataPrv->UserData = UserDataPtr; /* Set device as Disable */ DeviceDataPrv->UserEnabled = FALSE; /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_PORTD__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* Clear interrupt status flag - w1c */ PORTD_ISFR = PORT_ISFR_ISF(0x80); /* Initialization of Port Control registers */ /* PORTD_PCR7: ISF=0,IRQC=0,MUX=1 */ PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_IRQC(0x0F) | PORT_PCR_MUX(0x06) )) | (uint32_t)( PORT_PCR_MUX(0x01) )); /* NVIC_IPR7: PRI_31=0x80 */ NVIC_IPR7 = (uint32_t)((NVIC_IPR7 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_31(0x7F) )) | (uint32_t)( NVIC_IP_PRI_31(0x80) )); /* NVIC_ISER: SETENA|=0x80000000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x80000000); /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ExtIntLdd7_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
/* ===================================================================*/ LDD_TDeviceData * RTC1_Init(LDD_TUserData *UserDataPtr, bool SoftInit) { RTC1_TDeviceData *DevDataPtr; /* Allocate RTC device structure */ /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DevDataPtr = &DevDataPtr__DEFAULT_RTOS_ALLOC; DevDataPtr->UserDataPtr = UserDataPtr; /* Store the user data */ /* Allocate interrupt vector(s) */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_RTC__DEFAULT_RTOS_ISRPARAM = DevDataPtr; /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_RTC1_ID,DevDataPtr); /* Enable module clock */ /* SIM_SCGC6: RTC=1 */ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; if (!SoftInit) { RTC_SR = 0x00U; /* Disable counter */ RTC_TPR = RTC_TPR_TPR(0x00); /* Set prescaler register */ RTC_TSR = RTC_TSR_TSR(0x02); /* Set second register - 2000-01-01 0:0:1 */ RTC_TAR = RTC_TAR_TAR(0x00); /* Set alarm register - 2000-01-01 0:0:0 */ RTC_TCR = RTC_TCR_CIC(0x00) | RTC_TCR_TCV(0x00) | RTC_TCR_CIR(0x00) | RTC_TCR_TCR(0x00); /* Set compensation */ RTC_SR = RTC_SR_TCE_MASK; /* Enable counter */ } /* Enable interrupt */ /* RTC_IER: TAIE=1,TOIE=0,TIIE=0 */ RTC_IER = RTC_IER_TAIE_MASK; /* Enable interrupts */ /* NVICIP46: PRI46=0x70 */ NVICIP46 = NVIC_IP_PRI46(0x70); /* NVICISER1: SETENA|=0x4000 */ NVICISER1 |= NVIC_ISER_SETENA(0x4000); return DevDataPtr; }
/* ** =================================================================== ** Method : PE_low_level_init (component MKL26Z128FT4) ** ** Description : ** Initializes beans and provides common register initialization. ** The method is called automatically as a part of the ** application initialization code. ** This method is internal. It is used by Processor Expert only. ** =================================================================== */ void PE_low_level_init(void) { #ifdef PEX_RTOS_INIT PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */ #endif /* Initialization of the SIM module */ /* PORTA_PCR4: ISF=0,MUX=7 */ PORTA_PCR4 = (uint32_t)((PORTA_PCR4 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_MUX(0x07) )); /* Initialization of the FTFL_FlashConfig module */ /* Initialization of the PMC module */ /* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */ PMC_LVDSC1 = (uint8_t)((PMC_LVDSC1 & (uint8_t)~(uint8_t)( PMC_LVDSC1_LVDIE_MASK | PMC_LVDSC1_LVDV(0x03) )) | (uint8_t)( PMC_LVDSC1_LVDACK_MASK | PMC_LVDSC1_LVDRE_MASK )); /* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */ PMC_LVDSC2 = (uint8_t)((PMC_LVDSC2 & (uint8_t)~(uint8_t)( PMC_LVDSC2_LVWIE_MASK | PMC_LVDSC2_LVWV(0x03) )) | (uint8_t)( PMC_LVDSC2_LVWACK_MASK )); /* PMC_REGSC: BGEN=0,ACKISO=0,BGBE=0 */ PMC_REGSC &= (uint8_t)~(uint8_t)( PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK | PMC_REGSC_BGBE_MASK ); /* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */ SMC_PMPROT = 0x00U; /* Setup Power mode protection register */ /* Common initialization of the CPU registers */ /* PORTD_ISFR: ISF=0xD2 */ PORTD_ISFR = PORT_ISFR_ISF(0xD2); /* Common initialization of the CPU registers */ /* PORTD_PCR1: ISF=0,IRQC=0x0B,PE=1 */ PORTD_PCR1 = (uint32_t)((PORTD_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_IRQC(0x04) )) | (uint32_t)( PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK )); /* PORTD_PCR2: ISF=0,PE=1,PS=1 */ PORTD_PCR2 = (uint32_t)((PORTD_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_PE_MASK | PORT_PCR_PS_MASK )); /* PORTD_PCR4: ISF=0,IRQC=0x0B,PE=1 */ PORTD_PCR4 = (uint32_t)((PORTD_PCR4 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_IRQC(0x04) )) | (uint32_t)( PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK )); /* PORTD_PCR5: ISF=0,PE=1 */ PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_PE_MASK )); /* PORTD_PCR6: ISF=0,IRQC=0x0B,DSE=0,PE=1 */ PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_IRQC(0x04) | PORT_PCR_DSE_MASK )) | (uint32_t)( PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK )); /* PORTD_PCR7: ISF=0,IRQC=0x0B,DSE=0,PE=1 */ PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_IRQC(0x04) | PORT_PCR_DSE_MASK )) | (uint32_t)( PORT_PCR_IRQC(0x0B) | PORT_PCR_PE_MASK )); /* NVIC_ISER: SETENA|=0x80000040 */ NVIC_ISER |= NVIC_ISER_SETENA(0x80000040); /* NVIC_IPR7: PRI_31=0 */ NVIC_IPR7 &= (uint32_t)~(uint32_t)(NVIC_IP_PRI_31(0xFF)); /* PORTC_PCR3: ISF=0,PE=1 */ PORTC_PCR3 = (uint32_t)((PORTC_PCR3 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_PE_MASK )); /* PORTC_PCR5: ISF=0,PE=1,PS=1 */ PORTC_PCR5 = (uint32_t)((PORTC_PCR5 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_PE_MASK | PORT_PCR_PS_MASK )); /* NVIC_IPR5: PRI_21=0,PRI_20=0 */ NVIC_IPR5 &= (uint32_t)~(uint32_t)( NVIC_IP_PRI_21(0xFF) | NVIC_IP_PRI_20(0xFF) ); /* PORTB_PCR0: ISF=0,PE=1,PS=1 */ PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_PE_MASK | PORT_PCR_PS_MASK )); /* PORTB_PCR1: ISF=0,PE=1,PS=1 */ PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_PE_MASK | PORT_PCR_PS_MASK )); /* NVIC_IPR1: PRI_6=0 */ NVIC_IPR1 &= (uint32_t)~(uint32_t)(NVIC_IP_PRI_6(0xFF)); /* ### FreeRTOS "FRTOS1" init code ... */ #if configSYSTICK_USE_LOW_POWER_TIMER /* enable clocking for low power timer, otherwise vPortStopTickTimer() will crash */ SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* SIM_SCGC5: LPTMR=1 */ #endif vPortStopTickTimer(); /* tick timer shall not run until the RTOS scheduler is started */ /* ### Serial_LDD "IO1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)IO1_Init(NULL); /* ### Init_GPIO "PTD" init code ... */ PTD_Init(); /* ### BitIO_LDD "StartStopButton" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)StartStopButton_Init(NULL); /* ### BitIO_LDD "BitIoLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd1_Init(NULL); /* ### BitIO_LDD "BitIoLdd2" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd2_Init(NULL); /* ### BitIO_LDD "BitIoLdd3" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd3_Init(NULL); /* ### BitIO_LDD "BitIoLdd4" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd4_Init(NULL); /* ### BitIO_LDD "BitIoLdd5" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd5_Init(NULL); /* ### BitIO_LDD "ModeButton" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)ModeButton_Init(NULL); /* ### Init_GPIO "PTC" init code ... */ PTC_Init(); /* ### BitIO_LDD "BitIoLdd6" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd6_Init(NULL); /* ### BitIO_LDD "EncoderA" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)EncoderA_Init(NULL); /* ### BitIO_LDD "EncoderB" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)EncoderB_Init(NULL); /* ### BitIO_LDD "PreampEnable" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)PreampEnable_Init(NULL); /* ### Init_SRTC "RTC" init code ... */ RTC_Init(); /* ### Init_GPIO "PTB" init code ... */ PTB_Init(); /* ### DMATransfer_LDD "SSI1_TxDMA" component auto initialization. Auto initialization feature can be disabled by component's property "Auto initialization". */ (void)SSI1_TxDMA_Init(NULL); /* ### BitIO_LDD "BitIoLdd7" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd7_Init(NULL); }
/* ** =================================================================== ** Method : PE_low_level_init (component MK22FN1M0LH12) ** ** Description : ** Initializes beans and provides common register initialization. ** The method is called automatically as a part of the ** application initialization code. ** This method is internal. It is used by Processor Expert only. ** =================================================================== */ void PE_low_level_init(void) { #ifdef PEX_RTOS_INIT PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */ #endif /* Initialization of the SIM module */ /* PORTA_PCR4: ISF=0,MUX=7 */ PORTA_PCR4 = (uint32_t)((PORTA_PCR4 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_MUX(0x07) )); /* Initialization of the RCM module */ /* RCM_RPFW: RSTFLTSEL=0 */ RCM_RPFW &= (uint8_t)~(uint8_t)(RCM_RPFW_RSTFLTSEL(0x1F)); /* RCM_RPFC: RSTFLTSS=0,RSTFLTSRW=0 */ RCM_RPFC &= (uint8_t)~(uint8_t)( RCM_RPFC_RSTFLTSS_MASK | RCM_RPFC_RSTFLTSRW(0x03) ); /* SIM_SCGC7: MPU=1 */ SIM_SCGC7 |= SIM_SCGC7_MPU_MASK; /* Initialization of the MPU module */ /* MPU_CESR: SPERR=0,VLD=0 */ MPU_CESR &= (uint32_t)~(uint32_t)((MPU_CESR_SPERR(0x1F) | MPU_CESR_VLD_MASK)); /* Initialization of the PMC module */ /* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */ PMC_LVDSC1 = (uint8_t)((PMC_LVDSC1 & (uint8_t)~(uint8_t)( PMC_LVDSC1_LVDIE_MASK | PMC_LVDSC1_LVDV(0x03) )) | (uint8_t)( PMC_LVDSC1_LVDACK_MASK | PMC_LVDSC1_LVDRE_MASK )); /* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */ PMC_LVDSC2 = (uint8_t)((PMC_LVDSC2 & (uint8_t)~(uint8_t)( PMC_LVDSC2_LVWIE_MASK | PMC_LVDSC2_LVWV(0x03) )) | (uint8_t)( PMC_LVDSC2_LVWACK_MASK )); /* PMC_REGSC: BGEN=0,ACKISO=0,BGBE=0 */ PMC_REGSC &= (uint8_t)~(uint8_t)( PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK | PMC_REGSC_BGBE_MASK ); /* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */ SMC_PMPROT = 0x00U; /* Setup Power mode protection register */ /* Common initialization of the CPU registers */ /* NVICIP42: PRI42=0x80 */ NVICIP42 = NVIC_IP_PRI42(0x80); /* NVICIP53: PRI53=0 */ NVICIP53 = NVIC_IP_PRI53(0x00); /* NVICIP20: PRI20=0 */ NVICIP20 = NVIC_IP_PRI20(0x00); /* NVICISER1: SETENA|=0x0400 */ NVICISER1 |= NVIC_ISER_SETENA(0x0400); /* GPIOC_PDDR: PDD&=~0x0104 */ GPIOC_PDDR &= (uint32_t)~(uint32_t)(GPIO_PDDR_PDD(0x0104)); /* ### BitIO_LDD "BitIoLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd1_Init(NULL); /* ### BitIO_LDD "BitIoLdd2" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd2_Init(NULL); /* ### Init_FTM "FTM0" init code ... */ FTM0_Init(); /* ### SynchroMaster "SM1" init code ... */ SM1_Init(); /* ### BitIO_LDD "BitIoLdd4" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd4_Init(NULL); /* ### BitIO_LDD "BitIoLdd5" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd5_Init(NULL); /* ### ExtInt_LDD "ExtIntLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)ExtIntLdd1_Init(NULL); /* ### nRF24L01 "RF24" init code ... */ /* ### CriticalSection "CS1" init code ... */ /* ### Asynchro serial "AS1" init code ... */ AS1_Init(); /* ### KinetisSDK "KSDK1" init code ... */ /* Write code here ... */ /* ### Shell "mainShell" init code ... */ mainShell_Init(); /* initialize shell */ /* ### FreeRTOS "FRTOS1" init code ... */ #if configSYSTICK_USE_LOW_POWER_TIMER /* enable clocking for low power timer, otherwise vPortStopTickTimer() will crash */ SIM_PDD_SetClockGate(SIM_BASE_PTR, SIM_PDD_CLOCK_GATE_LPTMR0, PDD_ENABLE); #endif vPortStopTickTimer(); /* tick timer shall not run until the RTOS scheduler is started */ /* ### FreeRTOS_Tasks "rtTasks" init code ... */ rtTasks_CreateTasks(); /* ### BitIO_LDD "BitIoLdd6" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd6_Init(NULL); /* ### BitIO_LDD "BitIoLdd7" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd7_Init(NULL); /* ### BitIO_LDD "BitIoLdd8" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd8_Init(NULL); /* ### GenericSWSPI "RFIDspi" init code ... */ RFIDspi_Init(); /* ### BitIO_LDD "BitIoLdd9" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd9_Init(NULL); /* ### ExtInt_LDD "ExtIntLdd2" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)ExtIntLdd2_Init(NULL); /* ### BitIO_LDD "BitIoLdd10" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd10_Init(NULL); /* ### BitIO_LDD "BitIoLdd11" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd11_Init(NULL); /* ### LEDbit "LED1" init code ... */ LED1_Init(); /* initializes the driver */ /* ### BitIO_LDD "BitIoLdd3" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd3_Init(NULL); /* ### LEDbit "LED2" init code ... */ LED2_Init(); /* initializes the driver */ /* ### BitIO_LDD "BitIoLdd12" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */ (void)BitIoLdd12_Init(NULL); /* ### LEDbit "LED3" init code ... */ LED3_Init(); /* initializes the driver */ /* ### Init_USB_OTG "USB0" init code ... */ USB0_Init(); /* ### RingBuffer "Tx1" init code ... */ Tx1_Init(); /* ### RingBuffer "Rx1" init code ... */ Rx1_Init(); (void)USB1_Init(); }
/* ===================================================================*/ LDD_TDeviceData* SPI_SD_Init(LDD_TUserData *UserDataPtr) { /* Allocate LDD device structure */ SPI_SD_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */ /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_SPI1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; DeviceDataPrv->TxCommand = 0x80000000U; /* Initialization of current Tx command */ DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */ /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->CurrentAttributeSet = 0U; /* Init current attribute set */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ /* SIM_SCGC6: SPI1=1 */ SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK; /* Interrupt vector(s) priority setting */ /* NVICIP27: PRI27=0x70 */ NVICIP27 = NVIC_IP_PRI27(0x70); /* NVICISER0: SETENA|=0x08000000 */ NVICISER0 |= NVIC_ISER_SETENA(0x08000000); /* SIM_SCGC5: PORTD=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK; /* PORTD_PCR7: ISF=0,MUX=7 */ PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_MUX(0x07) )); /* PORTD_PCR6: ISF=0,MUX=7 */ PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_MUX(0x07) )); /* PORTD_PCR5: ISF=0,MUX=7 */ PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK )) | (uint32_t)( PORT_PCR_MUX(0x07) )); /* SPI1_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */ SPI1_MCR = SPI_MCR_DCONF(0x00) | SPI_MCR_ROOE_MASK | SPI_MCR_PCSIS(0x00) | SPI_MCR_SMPL_PT(0x00) | SPI_MCR_HALT_MASK; /* Set Configuration register */ /* SPI1_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=1,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */ SPI1_MCR = SPI_MCR_MSTR_MASK | SPI_MCR_DCONF(0x00) | SPI_MCR_ROOE_MASK | SPI_MCR_PCSIS(0x00) | SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK | SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK | SPI_MCR_SMPL_PT(0x00) | SPI_MCR_HALT_MASK; /* Set Configuration register */ /* SPI1_CTAR0: DBR=1,FMSZ=7,CPOL=0,CPHA=0,LSBFE=0,PCSSCK=0,PASC=0,PDT=0,PBR=0,CSSCK=0,ASC=0,DT=0,BR=0 */ SPI1_CTAR0 = SPI_CTAR_DBR_MASK | SPI_CTAR_FMSZ(0x07) | SPI_CTAR_PCSSCK(0x00) | SPI_CTAR_PASC(0x00) | SPI_CTAR_PDT(0x00) | SPI_CTAR_PBR(0x00) | SPI_CTAR_CSSCK(0x00) | SPI_CTAR_ASC(0x00) | SPI_CTAR_DT(0x00) | SPI_CTAR_BR(0x00); /* Set Clock and Transfer Attributes register */ /* SPI1_SR: TCF=1,TXRXS=0,??=0,EOQF=1,TFUF=1,??=0,TFFF=1,??=0,??=0,??=0,??=1,??=0,RFOF=1,??=0,RFDF=1,??=0,TXCTR=0,TXNXTPTR=0,RXCTR=0,POPNXTPTR=0 */ SPI1_SR = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TXCTR(0x00) | SPI_SR_TXNXTPTR(0x00) | SPI_SR_RXCTR(0x00) | SPI_SR_POPNXTPTR(0x00) | 0x00200000U; /* Clear flags */ /* SPI1_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SPI1_RSER = SPI_RSER_RFDF_RE_MASK; /* Set DMA Interrupt Request Select and Enable register */ SPI_SD_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Set Initial according speed CPU mode */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SPI_SD_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */ }
/* ===================================================================*/ LDD_TDeviceData* SS1_Init(LDD_TUserData *UserDataPtr) { /* Allocate LDD device structure */ SS1_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */ /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_SPI1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */ /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ /* SIM_SCGC4: SPI1=1 */ SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK; /* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=1,SSOE=0,LSBFE=0 */ SPI1_C1 = SPI_C1_CPHA_MASK; /* Clear control register */ /* Interrupt vector(s) priority setting */ /* NVIC_IPR2: PRI_11=0x80 */ NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_11(0x7F) )) | (uint32_t)( NVIC_IP_PRI_11(0x80) )); /* NVIC_ISER: SETENA|=0x0800 */ NVIC_ISER |= NVIC_ISER_SETENA(0x0800); /* PORTE_PCR3: ISF=0,MUX=5 */ PORTE_PCR3 = (uint32_t)((PORTE_PCR3 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x02) )) | (uint32_t)( PORT_PCR_MUX(0x05) )); /* PORTE_PCR1: ISF=0,MUX=5 */ PORTE_PCR1 = (uint32_t)((PORTE_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x02) )) | (uint32_t)( PORT_PCR_MUX(0x05) )); /* PORTE_PCR2: ISF=0,MUX=2 */ PORTE_PCR2 = (uint32_t)((PORTE_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* PORTE_PCR4: ISF=0,MUX=2 */ PORTE_PCR4 = (uint32_t)((PORTE_PCR4 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=0,SSOE=0,LSBFE=0 */ SPI1_C1 = 0x00U; /* Set Configuration register */ /* SPI1_C2: SPMIE=0,??=0,TXDMAE=0,MODFEN=0,BIDIROE=0,RXDMAE=0,SPISWAI=0,SPC0=0 */ SPI1_C2 = 0x00U; /* Set Configuration register */ /* SPI1_BR: ??=0,SPPR=0,SPR=0 */ SPI1_BR = (SPI_BR_SPPR(0x00) | SPI_BR_SPR(0x00)); /* Set baud rate register */ /* SPI1_C1: SPE=1 */ SPI1_C1 |= SPI_C1_SPE_MASK; /* Enable device */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SS1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */ }
/* ===================================================================*/ LDD_TDeviceData* AS1_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ AS1_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vectors */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_UART0_RX_TX__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_UART0_ERR__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC4: UART0=1 */ SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /* PORTB_PCR16: ISF=0,MUX=3 */ PORTB_PCR16 = (uint32_t)((PORTB_PCR16 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); /* PORTB_PCR17: ISF=0,MUX=3 */ PORTB_PCR17 = (uint32_t)((PORTB_PCR17 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); /* NVICIP16: PRI16=0x80 */ NVICIP16 = NVIC_IP_PRI16(0x80); /* NVICISER0: SETENA|=0x00010000 */ NVICISER0 |= NVIC_ISER_SETENA(0x00010000); /* NVICIP17: PRI17=0x80 */ NVICIP17 = NVIC_IP_PRI17(0x80); /* NVICISER0: SETENA|=0x00020000 */ NVICISER0 |= NVIC_ISER_SETENA(0x00020000); UART_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ /* UART0_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ UART0_C1 = 0x00U; /* Set the C1 register */ /* UART0_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */ UART0_C3 = 0x00U; /* Set the C3 register */ /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,BRFA=0 */ UART0_C4 = UART_C4_BRFA(0x00); /* Set the C4 register */ /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */ UART0_S2 = 0x00U; /* Set the S2 register */ /* UART0_MODEM: ??=0,??=0,??=0,??=0,RXRTSE=0,TXRTSPOL=0,TXRTSE=0,TXCTSE=0 */ UART0_MODEM = 0x00U; /* Set the MODEM register */ UART_PDD_SetBaudRateFineAdjust(UART0_BASE_PTR, 8u); /* Set baud rate fine adjust */ UART_PDD_SetBaudRate(UART0_BASE_PTR, 54U); /* Set the baud rate register. */ UART_PDD_EnableFifo(UART0_BASE_PTR, (UART_PDD_TX_FIFO_ENABLE | UART_PDD_RX_FIFO_ENABLE)); /* Enable RX and TX FIFO */ UART_PDD_FlushFifo(UART0_BASE_PTR, (UART_PDD_TX_FIFO_FLUSH | UART_PDD_RX_FIFO_FLUSH)); /* Flush RX and TX FIFO */ UART_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_ENABLE); /* Enable transmitter */ UART_PDD_EnableReceiver(UART0_BASE_PTR, PDD_ENABLE); /* Enable receiver */ UART_PDD_EnableInterrupt(UART0_BASE_PTR, ( UART_PDD_INTERRUPT_RECEIVER )); /* Enable interrupts */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_AS1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
/* ** =================================================================== ** Method : PWMMotor_Init (component TimerUnit_LDD) ** ** Description : ** Initializes the device. Allocates memory for the device data ** structure, allocates interrupt vectors and sets interrupt ** priority, sets pin routing, sets timing, etc. If the ** property <"Enable in init. code"> is set to "yes" value then ** the device is also enabled (see the description of the ** <Enable> method). In this case the <Enable> method is not ** necessary and needn't to be generated. This method can be ** called only once. Before the second call of Init the <Deinit> ** must be called first. ** Parameters : ** NAME - DESCRIPTION ** * UserDataPtr - Pointer to the user or ** RTOS specific data. This pointer will be ** passed as an event or callback parameter. ** Returns : ** --- - Pointer to the dynamically allocated ** private structure or NULL if there was an ** error. ** =================================================================== */ LDD_TDeviceData* PWMMotor_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ PWMMotor_TDeviceData *DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_FTM0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC6: FTM0=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; /* FTM0_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM0_MODE = FTM_MODE_WPDIS_MASK; /* Set up mode register */ /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM0_SC = 0x00U; /* Clear status and control register */ /* FTM0_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM0_CNTIN = 0x00U; /* Clear counter initial register */ /* FTM0_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM0_CNT = 0x00U; /* Reset counter register */ /* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C2SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C3SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C4SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C5SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C5SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C6SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C6SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C7SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C7SC = 0x00U; /* Clear channel status and control register */ /* FTM0_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x1388 */ FTM0_MOD = FTM_MOD_MOD(0x1388); /* Set up modulo register */ /* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ FTM0_C0SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* FTM0_C0V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0x03E8 */ FTM0_C0V = FTM_CnV_VAL(0x03E8); /* Set up channel value register */ /* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ FTM0_C3SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* FTM0_C3V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0x03E8 */ FTM0_C3V = FTM_CnV_VAL(0x03E8); /* Set up channel value register */ /* PORTC_PCR1: ISF=0,MUX=4 */ PORTC_PCR1 = (uint32_t)((PORTC_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTC_PCR4: ISF=0,MUX=4 */ PORTC_PCR4 = (uint32_t)((PORTC_PCR4 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); DeviceDataPrv->EnEvents = 0x0100U; /* Enable selected events */ /* NVICIP62: PRI62=0x80 */ NVICIP62 = NVIC_IP_PRI62(0x80); /* NVICISER1: SETENA|=0x40000000 */ NVICISER1 |= NVIC_ISER_SETENA(0x40000000); /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=1,CPWMS=0,CLKS=1,PS=0 */ FTM0_SC = (FTM_SC_TOIE_MASK | FTM_SC_CLKS(0x01)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_PWMMotor_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* ===================================================================*/ LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr) { TU1_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) { /* Allocate device structure */ /* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* Interrupt vector(s) allocation */ /* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */ /* Note: Exception handler for interrupt is not saved, because it is not modified */ DeviceDataPrv->SavedISRSettings_TUInterrupt.isrData = _int_get_isr_data(LDD_ivIndex_INT_FTM0); DeviceDataPrv->SavedISRSettings_TUInterrupt.isrFunction = _int_install_isr(LDD_ivIndex_INT_FTM0, TU1_Interrupt, DeviceDataPrv); /* SIM_SCGC6: FTM0=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; /* FTM0_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM0_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */ /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM0_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */ /* FTM0_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM0_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */ /* FTM0_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM0_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */ /* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C2SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C3SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C4SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C5SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C5SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C6SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C6SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C7SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C7SC = 0x00U; /* Clear channel status and control register */ /* FTM0_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x927B */ FTM0_MOD = FTM_MOD_MOD(0x927B); /* Set up modulo register */ DeviceDataPrv->EnEvents = 0x0100U; /* Enable selected events */ /* NVICIP42: PRI42=0x70 */ NVICIP42 = NVIC_IP_PRI42(0x70); /* NVICISER1: SETENA|=0x0400 */ NVICISER1 |= NVIC_ISER_SETENA(0x0400); /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=1,CPWMS=0,CLKS=1,PS=4 */ FTM0_SC = (FTM_SC_TOIE_MASK | FTM_SC_CLKS(0x01) | FTM_SC_PS(0x04)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* ===================================================================*/ LDD_TDeviceData* ETH1_Init(LDD_TUserData *UserDataPtr) { ETH1_TDeviceData *DeviceDataPrv; ETH1_TTxQueueItem *TxQueueItemPtr; ETH1_TRxQueueItem *RxQueueItemPtr; uint8_t* MemPtr; /* Allocate internal device data structure */ /* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->DuplexMode = LDD_ETH_FULL_DUPLEX; /* Store duplex mode configuration */ DeviceDataPrv->FilterMode = LDD_ETH_ACCEPT_BC; /* Store filter mode configuration */ DeviceDataPrv->SleepMode = LDD_ETH_DISABLED; /* Store sleep mode configuration */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->Index = 0U; /* Set the component instance index */ DeviceDataPrv->EventMask = /* Initialize the event mask */ LDD_ETH_ON_FRAME_TRANSMITTED | LDD_ETH_ON_FRAME_RECEIVED | LDD_ETH_ON_FATAL_ERROR |0U; DeviceDataPrv->EnabledMode = TRUE; /* Enable the device clock configuration */ /* SIM_SCGC2: ENET=1 */ SIM_SCGC2 |= SIM_SCGC2_ENET_MASK; ENET_PDD_DisableDevice(ENET_BASE_PTR); DeviceDataPrv->Enabled = FALSE; ENET_PDD_EnableMIBCounters(ENET_BASE_PTR, FALSE); /* Disable statistic counters */ ENET_PDD_ClearMIBCounters(ENET_BASE_PTR); /* Clear statistic counters */ ENET_PDD_EnableMIBCounters(ENET_BASE_PTR, TRUE); /* Enable statistic counters */ /* Set pin assignments */ /* PORTB_PCR1: ISF=0,MUX=4 */ PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTB_PCR0: ISF=0,MUX=4 */ PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTA_PCR18: ISF=0,MUX=0 */ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* PORTA_PCR16: ISF=0,MUX=4 */ PORTA_PCR16 = (uint32_t)((PORTA_PCR16 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTA_PCR17: ISF=0,MUX=4 */ PORTA_PCR17 = (uint32_t)((PORTA_PCR17 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTA_PCR15: ISF=0,MUX=4 */ PORTA_PCR15 = (uint32_t)((PORTA_PCR15 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTA_PCR14: ISF=0,MUX=4 */ PORTA_PCR14 = (uint32_t)((PORTA_PCR14 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTA_PCR13: ISF=0,MUX=4 */ PORTA_PCR13 = (uint32_t)((PORTA_PCR13 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTA_PCR12: ISF=0,MUX=4 */ PORTA_PCR12 = (uint32_t)((PORTA_PCR12 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* Set interrupt priorities */ /* NVICIP76: PRI76=0x80 */ NVICIP76 = NVIC_IP_PRI76(0x80); /* NVICISER2: SETENA|=0x1000 */ NVICISER2 |= NVIC_ISER_SETENA(0x1000); /* NVICIP77: PRI77=0x80 */ NVICIP77 = NVIC_IP_PRI77(0x80); /* NVICISER2: SETENA|=0x2000 */ NVICISER2 |= NVIC_ISER_SETENA(0x2000); /* NVICIP78: PRI78=0x80 */ NVICIP78 = NVIC_IP_PRI78(0x80); /* NVICISER2: SETENA|=0x4000 */ NVICISER2 |= NVIC_ISER_SETENA(0x4000); /* Set interrupt mask */ /* ENET_EIMR: ??=0,BABR=0,BABT=0,GRA=0,TXF=1,TXB=0,RXF=1,RXB=0,MII=0,EBERR=1,LC=0,RL=0,UN=0,PLR=0,WAKEUP=0,TS_AVAIL=0,TS_TIMER=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ ENET_EIMR = (ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK); /* Clear interrupt flags */ /* ENET_EIR: ??=1,BABR=1,BABT=1,GRA=1,TXF=1,TXB=1,RXF=1,RXB=1,MII=1,EBERR=1,LC=1,RL=1,UN=1,PLR=0,WAKEUP=0,TS_AVAIL=0,TS_TIMER=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ ENET_EIR = ENET_EIR_BABR_MASK | ENET_EIR_BABT_MASK | ENET_EIR_GRA_MASK | ENET_EIR_TXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_RXB_MASK | ENET_EIR_MII_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_LC_MASK | ENET_EIR_RL_MASK | ENET_EIR_UN_MASK | 0x80000000U; /* Allocate the transmit frame interrupt vector */ /* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_ENET_Transmit__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv; /* Allocate the receive frame interrupt vector */ /* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_ENET_Receive__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv; /* Allocate the shared interrupt vector */ /* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_ENET_Error__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv; /* Set MAC address */ /* ENET_PALR: PADDR1=0x43EF783A */ ENET_PALR = ENET_PALR_PADDR1(0x43EF783A); /* ENET_PAUR: PADDR2=0x2E19,TYPE=0 */ ENET_PAUR = (ENET_PAUR_PADDR2(0x2E19) | ENET_PAUR_TYPE(0x00)); /* Set unicast address hash table */ /* ENET_IAUR: IADDR1=0 */ ENET_IAUR = ENET_IAUR_IADDR1(0x00); /* ENET_IALR: IADDR2=0 */ ENET_IALR = ENET_IALR_IADDR2(0x00); /* Set multicast address hash table */ /* ENET_GAUR: GADDR1=0 */ ENET_GAUR = ENET_GAUR_GADDR1(0x00); /* ENET_GALR: GADDR2=0 */ ENET_GALR = ENET_GALR_GADDR2(0x00); /* Set PAUSE frame duration */ /* ENET_OPD: OPCODE=0,PAUSE_DUR=0 */ ENET_OPD = (ENET_OPD_OPCODE(0x00) | ENET_OPD_PAUSE_DUR(0x00)); /* Set transmit control register */ /* ENET_TCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CRCFWD=0,ADDINS=0,ADDSEL=0,RFC_PAUSE=0,TFC_PAUSE=0,FDEN=1,??=0,GTS=0 */ ENET_TCR = (ENET_TCR_ADDSEL(0x00) | ENET_TCR_FDEN_MASK); /* Set transmit accelerator function configuration register */ /* ENET_TACC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PROCHK=0,IPCHK=0,??=0,??=0,SHIFT16=0 */ ENET_TACC = 0x00U; /* Set receive control register */ /* ENET_RCR: GRS=0,NLC=0,MAX_FL=0x05EE,CFEN=0,CRCFWD=0,PAUFWD=1,PADEN=0,??=0,??=0,RMII_10T=0,RMII_MODE=1,??=0,??=0,FCE=1,BC_REJ=0,PROM=0,MII_MODE=1,DRT=0,LOOP=0 */ ENET_RCR = ENET_RCR_MAX_FL(0x05EE) | ENET_RCR_PAUFWD_MASK | ENET_RCR_RMII_MODE_MASK | ENET_RCR_FCE_MASK | ENET_RCR_MII_MODE_MASK; /* Set receive accelerator function configuration register */ /* ENET_RACC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,SHIFT16=0,LINEDIS=0,??=0,??=0,??=0,PRODIS=0,IPDIS=0,PADREM=0 */ ENET_RACC = 0x00U; /* Set transmit inter-packet gap */ /* ENET_TIPG: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,IPG=8 */ ENET_TIPG = ENET_TIPG_IPG(0x08); /* Set frame truncation length */ /* ENET_FTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TRUNC_FL=0x0800 */ ENET_FTRL = ENET_FTRL_TRUNC_FL(0x0800); /* Set transmit FIFO watermark */ /* ENET_TFWR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,STRFWD=1,??=0,??=0,TFWR=0 */ ENET_TFWR = (ENET_TFWR_STRFWD_MASK | ENET_TFWR_TFWR(0x00)); /* Set transmit FIFO section empty threshold */ /* ENET_TSEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_SECTION_EMPTY=0 */ ENET_TSEM = ENET_TSEM_TX_SECTION_EMPTY(0x00); /* Set transmit FIFO almost empty threshold */ /* ENET_TAEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_ALMOST_EMPTY=8 */ ENET_TAEM = ENET_TAEM_TX_ALMOST_EMPTY(0x08); /* Set transmit FIFO almost full threshold */ /* ENET_TAFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_ALMOST_FULL=8 */ ENET_TAFL = ENET_TAFL_TX_ALMOST_FULL(0x08); /* Set receive FIFO section full threshold */ /* ENET_RSFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_SECTION_FULL=0 */ ENET_RSFL = ENET_RSFL_RX_SECTION_FULL(0x00); /* Set receive FIFO section empty threshold */ /* ENET_RSEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_SECTION_EMPTY=0 */ ENET_RSEM = ENET_RSEM_RX_SECTION_EMPTY(0x00); /* Set receive FIFO almost empty threshold */ /* ENET_RAEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_ALMOST_EMPTY=8 */ ENET_RAEM = ENET_RAEM_RX_ALMOST_EMPTY(0x08); /* Set receive FIFO almost full threshold */ /* ENET_RAFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_ALMOST_FULL=8 */ ENET_RAFL = ENET_RAFL_RX_ALMOST_FULL(0x08); /* Set MII speed control register */ /* ENET_MSCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HOLDTIME=7,DIS_PRE=1,MII_SPEED=3,??=0 */ ENET_MSCR = ENET_MSCR_HOLDTIME(0x07) | ENET_MSCR_DIS_PRE_MASK | ENET_MSCR_MII_SPEED(0x03); /* Set receive buffer size */ /* ENET_MRBR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,R_BUF_SIZE=0,??=0,??=0,??=0,??=0 */ ENET_MRBR = ENET_MRBR_R_BUF_SIZE(0x00); /* Initialize the transmit frame buffer queue */ LDD_QUEUE_INIT(ETH1_TTxQueueItem, DeviceDataPrv->TxQueue, ETH1_QUEUE_MEM_ALIGN); /* Initialize the queue data structure */ TxQueueItemPtr = LDD_QUEUE_GET_DATA_START(DeviceDataPrv->TxQueue); while (TxQueueItemPtr != (LDD_QUEUE_GET_DATA_END(DeviceDataPrv->TxQueue) + 1)) { /* Clear queue item */ for (MemPtr = (uint8_t*)(uint32_t)TxQueueItemPtr; MemPtr != (uint8_t*)(uint32_t)(TxQueueItemPtr + 1); MemPtr++) { *MemPtr = 0U; } TxQueueItemPtr++; /* Move to the next queue item */ } setReg32(ENET_TDSR, LDD_QUEUE_GET_DATA_START(DeviceDataPrv->TxQueue)); /* Initialize the receive frame buffer queue */ LDD_QUEUE_INIT(ETH1_TRxQueueItem, DeviceDataPrv->RxQueue, ETH1_QUEUE_MEM_ALIGN); /* Initialize the queue data structure */ RxQueueItemPtr = LDD_QUEUE_GET_DATA_START(DeviceDataPrv->RxQueue); while (RxQueueItemPtr != (LDD_QUEUE_GET_DATA_END(DeviceDataPrv->RxQueue) + 1)) { /* Clear queue item */ for (MemPtr = (uint8_t*)(uint32_t)RxQueueItemPtr; MemPtr != (uint8_t*)(uint32_t)(RxQueueItemPtr + 1); MemPtr++) { *MemPtr = 0U; } RxQueueItemPtr++; /* Move to the next queue item */ } setReg32(ENET_RDSR, LDD_QUEUE_GET_DATA_START(DeviceDataPrv->RxQueue)); /* ENET_ECR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DBSWP=0,STOPEN=0,DBGEN=0,??=0,EN1588=0,SLEEP=0,MAGICEN=0,ETHEREN=0,RESET=0 */ ENET_ECR = 0x00U; /* Enable the device */ ENET_PDD_EnableDevice(ENET_BASE_PTR); DeviceDataPrv->Enabled = TRUE; /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ETH1_ID,DeviceDataPrv); return (LDD_TDeviceData*)DeviceDataPrv; }
/* ===================================================================*/ LDD_TDeviceData* ASerialLdd1_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ ASerialLdd1_TDeviceDataPtr DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vectors */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_UART0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC4: UART0=1 */ SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /* PORTA_PCR1: ISF=0,MUX=2 */ PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* PORTA_PCR2: ISF=0,MUX=2 */ PORTA_PCR2 = (uint32_t)((PORTA_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x05) )) | (uint32_t)( PORT_PCR_MUX(0x02) )); /* NVIC_IPR3: PRI_12=0 */ NVIC_IPR3 &= (uint32_t)~(uint32_t)(NVIC_IP_PRI_12(0xFF)); /* NVIC_ISER: SETENA|=0x1000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x1000); UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ DeviceDataPrv->ErrFlag = 0x00U; /* Reset error flags */ DeviceDataPrv->EnUser = FALSE; /* Disable device */ /* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ UART0_C1 = 0x00U; /* Set the C1 register */ /* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */ UART0_C3 = 0x00U; /* Set the C3 register */ /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */ UART0_C4 = UART0_C4_OSR(0x00); /* Set the C4 register */ /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */ UART0_S2 = 0x00U; /* Set the S2 register */ SIM_PDD_SetClockSourceUART0(SIM_BASE_PTR, SIM_PDD_UART0_PLL_FLL_CLOCK); UART0_PDD_SetBaudRate(UART0_BASE_PTR, 2U); /* Set the baud rate register. */ UART0_PDD_SetOversamplingRatio(UART0_BASE_PTR, 3U); UART0_PDD_EnableSamplingOnBothEdges(UART0_BASE_PTR, PDD_ENABLE); UART0_PDD_DisableInterrupt(UART0_BASE_PTR, ( UART0_PDD_INTERRUPT_RECEIVER | UART0_PDD_INTERRUPT_TRANSMITTER | UART0_PDD_INTERRUPT_PARITY_ERROR | UART0_PDD_INTERRUPT_FRAMING_ERROR | UART0_PDD_INTERRUPT_NOISE_ERROR | UART0_PDD_INTERRUPT_OVERRUN_ERROR )); /* Disable interrupts */ UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ASerialLdd1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }
/* ===================================================================*/ LDD_TDeviceData* UART_A_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ UART_A_TDeviceDataPtr DeviceDataPrv; /* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; /* Clear the receive counters and pointer */ DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */ DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */ DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */ /* Clear the transmit counters and pointer */ DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */ DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */ DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */ DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Allocate interrupt vectors */ /* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */ /* Note: Exception handler for interrupt is not saved, because it is not modified */ DeviceDataPrv->SavedISRSettings.isrData = _int_get_isr_data(LDD_ivIndex_INT_UART3_RX_TX); DeviceDataPrv->SavedISRSettings.isrFunction = _int_install_isr(LDD_ivIndex_INT_UART3_RX_TX, UART_A_Interrupt, DeviceDataPrv); /* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */ /* Note: Exception handler for interrupt is not saved, because it is not modified */ DeviceDataPrv->SavedISRSettings.isrData = _int_get_isr_data(LDD_ivIndex_INT_UART3_ERR); DeviceDataPrv->SavedISRSettings.isrFunction = _int_install_isr(LDD_ivIndex_INT_UART3_ERR, UART_A_Interrupt, DeviceDataPrv); /* SIM_SCGC4: UART3=1 */ SIM_SCGC4 |= SIM_SCGC4_UART3_MASK; /* SIM_SCGC5: PORTC=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK; /* PORTC_PCR16: ISF=0,MUX=3 */ PORTC_PCR16 = (uint32_t)((PORTC_PCR16 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); /* PORTC_PCR17: ISF=0,MUX=3 */ PORTC_PCR17 = (uint32_t)((PORTC_PCR17 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); /* NVICIP37: PRI37=0x70 */ NVICIP37 = NVIC_IP_PRI37(0x70); /* NVICISER1: SETENA|=0x20 */ NVICISER1 |= NVIC_ISER_SETENA(0x20); /* NVICIP38: PRI38=0x70 */ NVICIP38 = NVIC_IP_PRI38(0x70); /* NVICISER1: SETENA|=0x40 */ NVICISER1 |= NVIC_ISER_SETENA(0x40); UART_PDD_EnableTransmitter(UART3_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */ UART_PDD_EnableReceiver(UART3_BASE_PTR, PDD_DISABLE); /* Disable receiver. */ DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */ /* UART3_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ UART3_C1 = 0x00U; /* Set the C1 register */ /* UART3_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */ UART3_C3 = 0x00U; /* Set the C3 register */ /* UART3_C4: MAEN1=0,MAEN2=0,M10=0,BRFA=0 */ UART3_C4 = UART_C4_BRFA(0x00); /* Set the C4 register */ /* UART3_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */ UART3_S2 = 0x00U; /* Set the S2 register */ /* UART3_MODEM: ??=0,??=0,??=0,??=0,RXRTSE=0,TXRTSPOL=0,TXRTSE=0,TXCTSE=0 */ UART3_MODEM = 0x00U; /* Set the MODEM register */ UART_PDD_SetBaudRateFineAdjust(UART3_BASE_PTR, 18u); /* Set baud rate fine adjust */ UART_PDD_SetBaudRate(UART3_BASE_PTR, 32U); /* Set the baud rate register. */ UART_PDD_EnableFifo(UART3_BASE_PTR, (UART_PDD_TX_FIFO_ENABLE | UART_PDD_RX_FIFO_ENABLE)); /* Enable RX and TX FIFO */ UART_PDD_FlushFifo(UART3_BASE_PTR, (UART_PDD_TX_FIFO_FLUSH | UART_PDD_RX_FIFO_FLUSH)); /* Flush RX and TX FIFO */ UART_PDD_EnableTransmitter(UART3_BASE_PTR, PDD_ENABLE); /* Enable transmitter */ UART_PDD_EnableReceiver(UART3_BASE_PTR, PDD_ENABLE); /* Enable receiver */ UART_PDD_EnableInterrupt(UART3_BASE_PTR, ( UART_PDD_INTERRUPT_RECEIVER )); /* Enable interrupts */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_UART_A_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); }