static Bool
riva_is_connected(struct riva_par *par, Bool second)
{
volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0;
U032 reg52C, reg608;
Bool present;
if(second) PRAMDAC += 0x800;
reg52C = NV_RD32(PRAMDAC, 0x052C);
reg608 = NV_RD32(PRAMDAC, 0x0608);
NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
mdelay(1);
NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140);
NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000);
mdelay(1);
present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE;
NV_WR32(par->riva.PRAMDAC0, 0x0608,
NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF);
NV_WR32(PRAMDAC, 0x052C, reg52C);
NV_WR32(PRAMDAC, 0x0608, reg608);
return present;
}
static int nvidia_bl_update_status(struct backlight_device *bd)
{
struct nvidia_par *par = bl_get_data(bd);
u32 tmp_pcrt, tmp_pmc, fpcontrol;
int level;
if (!par->FlatPanel)
return 0;
if (bd->props.power != FB_BLANK_UNBLANK ||
bd->props.fb_blank != FB_BLANK_UNBLANK)
level = 0;
else
level = bd->props.brightness;
tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
if (level > 0) {
tmp_pcrt |= 0x1;
tmp_pmc |= (1 << 31); /* backlight bit */
tmp_pmc |= nvidia_bl_get_level_brightness(par, level) << 16;
fpcontrol |= par->fpSyncs;
} else
fpcontrol |= 0x20000022;
NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
NV_WR32(par->PMC, 0x10F0, tmp_pmc);
NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
return 0;
}
static void
riva_is_second(struct riva_par *par)
{
if (par->FlatPanel == 1) {
switch(par->Chipset & 0xffff) {
case 0x0174:
case 0x0175:
case 0x0176:
case 0x0177:
case 0x0179:
case 0x017C:
case 0x017D:
case 0x0186:
case 0x0187:
/* this might not be a good default for the chips below */
case 0x0286:
case 0x028C:
case 0x0316:
case 0x0317:
case 0x031A:
case 0x031B:
case 0x031C:
case 0x031D:
case 0x031E:
case 0x031F:
case 0x0324:
case 0x0325:
case 0x0328:
case 0x0329:
case 0x032C:
case 0x032D:
par->SecondCRTC = TRUE;
break;
default:
par->SecondCRTC = FALSE;
break;
}
} else {
if(riva_is_connected(par, 0)) {
if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100)
par->SecondCRTC = TRUE;
else
par->SecondCRTC = FALSE;
} else
if (riva_is_connected(par, 1)) {
if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100)
par->SecondCRTC = TRUE;
else
par->SecondCRTC = FALSE;
} else /* default */
par->SecondCRTC = FALSE;
}
riva_override_CRTC(par);
}
static void nv4GetConfig(struct nvidia_par *par)
{
if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
par->RamAmountKBytes =
((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
1024 * 2;
} else {
static void
nvc0_graph_load_microcode()
{
int i;
const uint32_t val260 = NV_RD32(0x260);
printf("micro code loading...\n");
NV_WR32(0x260, val260 & ~1);
#ifdef USE_BLOB_UCODE
printf("use blob_ucode^\n");
/* load HUB microcode */
NV_WR32(0x4091c0, 0x01000000);
for (i = 0; i< sizeof(nvc0_grhub_data) /4; i++){
NV_WR32(0x4091c4,((uint32_t *)nvc0_grhub_data)[i]);
}
NV_WR32(0x409180,0x01000000);
for (i = 0; i< sizeof(nvc0_grhub_code) /4; i++){
if ((i & 0x3f) == 0){
NV_WR32(0x409188, i>>6);
}
//NV_WR32(NVC0_CTXCTL_FUC_CODE_DATA, x);
NV_WR32(0x409184,((uint32_t *)nvc0_grhub_code)[i]);
}
void nv50_graph_reset() {
uint32_t enable = NV_RD32(0x200);
NV_WR32(0x200, enable & ~0x1000);
NV_WR32(0x200, enable | 0x1000);
NV_WR32(0x400040, -1);
NV_WR32(0x400040, 0);
}
unsigned long riva_get_memlen(struct riva_par *par)
{
RIVA_HW_INST *chip = &par->riva;
unsigned long memlen = 0;
unsigned int chipset = par->Chipset;
struct pci_dev* dev;
u32 amt;
switch (chip->Architecture) {
case NV_ARCH_03:
if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
&& ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) {
/*
* SDRAM 128 ZX.
*/
switch (NV_RD32(chip->PFB,0x00000000) & 0x03) {
case 2:
memlen = 1024 * 4;
break;
case 1:
memlen = 1024 * 2;
break;
default:
memlen = 1024 * 8;
break;
}
} else {
memlen = 1024 * 8;
}
} else {
/*
* SGRAM 128.
*/
switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
case 0:
memlen = 1024 * 8;
break;
case 2:
memlen = 1024 * 4;
break;
default:
memlen = 1024 * 2;
break;
}
}
break;
case NV_ARCH_04:
if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) {
memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) *
1024 * 2 + 1024 * 2;
} else {
switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
static int NVIsConnected(struct nvidia_par *par, int output)
{
volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
u32 reg52C, reg608, dac0_reg608 = 0;
int present;
if (output) {
dac0_reg608 = NV_RD32(PRAMDAC, 0x0608);
PRAMDAC += 0x800;
}
reg52C = NV_RD32(PRAMDAC, 0x052C);
reg608 = NV_RD32(PRAMDAC, 0x0608);
NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
msleep(1);
NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
0x00001000);
msleep(1);
present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
if (present)
printk("nvidiafb: CRTC%i analog found\n", output);
else
printk("nvidiafb: CRTC%i analog not found\n", output);
if (output)
NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
NV_WR32(PRAMDAC, 0x052C, reg52C);
NV_WR32(PRAMDAC, 0x0608, reg608);
return present;
}
