CBOOL NX_LVDS_InitRegTest( U32 ModuleIndex )
{
register NX_LVDS_RegisterSet* pRegister;
register U32 regvalue;
NX_ASSERT( NUMBER_OF_LVDS_MODULE > ModuleIndex );
NX_ASSERT( CNULL != __g_pRegister[ModuleIndex] );
pRegister = __g_pRegister[ModuleIndex];
U32 fail = 0;
WriteIODW(&pRegister->LVDSCTRL0, 0x07fffE);
regvalue = ReadIODW(&pRegister->LVDSCTRL0);
if( regvalue != 0x07fffE )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSCTRL0 regvalue = %x, Golden ( 0x07fffE )", regvalue);
}
WriteIODW(&pRegister->LVDSCTRL1, 0x03ffff);
regvalue = ReadIODW(&pRegister->LVDSCTRL1);
if( regvalue != 0x03ffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSCTRL1 regvalue = %x, Golden ( 0x03ffff )", regvalue);
}
WriteIODW(&pRegister->LVDSCTRL2, 0x0ffff);
regvalue = ReadIODW(&pRegister->LVDSCTRL2);
if( regvalue != 0x0ffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSCTRL2 regvalue = %x, Golden ( 0x0ffff )", regvalue);
}
WriteIODW(&pRegister->LVDSCTRL3, 0x03ff);
regvalue = ReadIODW(&pRegister->LVDSCTRL3);
if( regvalue != 0x03ff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSCTRL3 regvalue = %x, Golden ( 0x03ff )", regvalue);
}
WriteIODW(&pRegister->LVDSCTRL4, 0x1fffffff);
regvalue = ReadIODW(&pRegister->LVDSCTRL4);
if( regvalue != 0x1fffffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSCTRL4 regvalue = %x, Golden ( 0x1fffffff )", regvalue);
}
//@added choiyk 2012-12-17 ¿ÀÀü 11:21:54
WriteIODW(&pRegister->LVDSLOC0, (pow(2,30)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOC0);
if( regvalue != 0x3fffffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOC0 regvalue = %x, Golden ( %x )", regvalue, 0x3fffffff );
}
WriteIODW(&pRegister->LVDSLOC1, (pow(2,30)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOC1);
if( regvalue != 0x3fffffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOC1 regvalue = %x, Golden ( %x )", regvalue, 0x3fffffff );
}
WriteIODW(&pRegister->LVDSLOC2, (pow(2,30)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOC2);
if( regvalue != 0x3fffffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOC2 regvalue = %x, Golden ( %x )", regvalue, 0x3fffffff );
}
WriteIODW(&pRegister->LVDSLOC3, (pow(2,30)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOC3);
if( regvalue != 0x3fffffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOC3 regvalue = %x, Golden ( %x )", regvalue, 0x3fffffff );
}
WriteIODW(&pRegister->LVDSLOC4, (pow(2,30)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOC4);
if( regvalue != 0x3fffffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOC4 regvalue = %x, Golden ( %x )", regvalue, 0x3fffffff );
}
WriteIODW(&pRegister->LVDSLOC5, (pow(2,30)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOC5);
if( regvalue != 0x3fffffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOC5 regvalue = %x, Golden ( %x )", regvalue, 0x3fffffff );
}
WriteIODW(&pRegister->LVDSLOC6, (pow(2,30)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOC6);
if( regvalue != 0x3fffffff )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOC6 regvalue = %x, Golden ( %x )", regvalue, 0x3fffffff );
}
WriteIODW(&pRegister->LVDSLOCMASK0, (pow(2,32)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOCMASK0);
if( regvalue != (pow(2,32)-1) )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOCMASK0 regvalue = %x, Golden ( %x )", regvalue, (pow(2,32)-1));
}
WriteIODW(&pRegister->LVDSLOCMASK1, 7 );
regvalue = ReadIODW(&pRegister->LVDSLOCMASK1);
if( regvalue != 7 )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] regvalue = %x, Golden ( %x )", regvalue, 7 );
}
WriteIODW(&pRegister->LVDSLOCPOL0, (pow(2,32)-1) );
regvalue = ReadIODW(&pRegister->LVDSLOCPOL0);
if( regvalue != (pow(2,32)-1) )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOCPOL0 regvalue = %x, Golden ( %x )", regvalue, (pow(2,32)-1));
}
WriteIODW(&pRegister->LVDSLOCPOL1, 7 );
regvalue = ReadIODW(&pRegister->LVDSLOCPOL1);
if( regvalue != 7 )
{
fail = 1; //return CFALSE;
NX_CONSOLE_Printf("\n[DEBUG] LVDSLOCPOL1 regvalue = %x, Golden ( %x )", regvalue, 7 );
}
if( fail == 1 )
{
return CFALSE;
}
return CTRUE; // CTRUE
}
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
//reset
//1. ohci
writel(readl(0xc0011014) & ~(1<<18), 0xc0011014);
//2. auxwell
writel(readl(0xc0011014) & ~(1<<19), 0xc0011014);
//3. ahb
writel(readl(0xc0011014) & ~(1<<17), 0xc0011014);
//4. hsic utmi
writel(readl(0xc0011014) & ~(1<<22), 0xc0011014);
//5. ehci utmi
writel(readl(0xc0011014) & ~(1<<21), 0xc0011014);
//6. free
writel(readl(0xc0011014) & ~(1<<20), 0xc0011014);
//7. hsic por
writel(readl(0xc0011028) | (3<<18), 0xc0011028);
//8. echi por
writel(readl(0xc0011020) | (3<<7 ), 0xc0011020);
//9. resetcon
writel(readl(0xc0012004) & ~(1<<24), 0xc0012004); // reset on
#if defined( CONFIG_USB_HSIC_MODE )
// GPIO Reset
NX_GPIO_SetPadFunction( 4, 22, 0 );
NX_GPIO_SetOutputEnable( 4, 22, CTRUE );
#if defined( CONFIG_MACH_S5P4418 )
NX_GPIO_SetPullSelect( 4, 22, CTRUE );
NX_GPIO_SetPullEnable( 4, 22, CFALSE );
#else
NX_GPIO_SetPullEnable( 4, 22, NX_GPIO_PULL_UP );
#endif
NX_GPIO_SetOutputValue( 4, 22, CTRUE );
udelay( 100 );
NX_GPIO_SetOutputValue( 4, 22, CFALSE );
udelay( 100 );
NX_GPIO_SetOutputValue( 4, 22, CTRUE );
#endif
// Release common reset of host controller
writel(readl(0xc0012004) | (1<<24), 0xc0012004); // reset off
NX_CONSOLE_Printf( "\nRSTCON[24](0xc0012004) set 1'b1 0x%08x\n", readl( 0xc0012004 ) );
#if defined( CONFIG_USB_HSIC_MODE )
// HSIC 12M rerference Clock setting
writel( 0x02, 0xc006b000 );
writel( 0x0C, 0xc006b004 ); // 8 : ok, c : no
writel( 0x10, 0xc006b00c );
writel( 0x30, 0xc006b00c );
writel( 0x06, 0xc006b000 );
// HSIC 480M clock setting
writel(readl(0xc0011014) & ~(3<<23), 0xc0011014);
writel(readl(0xc0011014) | (2<<23), 0xc0011014);
// 2. HSIC Enable in PORT1 of LINK
writel(readl(0xc0011014) & ~(7<<14), 0xc0011014);
writel(readl(0xc0011014) | (2<<14), 0xc0011014);
#endif
// Program AHB Burst type
writel(readl(0xc001101c) & ~(7<<25), 0xc001101c);
writel(readl(0xc001101c) | (7<<25), 0xc001101c);
NX_CONSOLE_Printf( "TIEOFFREG7[27:25](0xc001101c) set 3'b111 0x%08x\n", readl( 0xc001101c ) );
// Select word interface and enable word interface selection in link
writel(readl(0xc0011014) & ~(3<<25), 0xc0011014);
writel(readl(0xc0011014) | (3<<25), 0xc0011014); // 2'b01 8bit, 2'b11 16bit word
NX_CONSOLE_Printf( "TIEOFFREG5[26:25](0xc0011014) set 2'b11 0x%08x\n", readl( 0xc0011014 ) );
// Select word interface and enable word interface selection in link in EHCI PHY
writel(readl(0xc0011024) & ~(3<<8), 0xc0011024);
writel(readl(0xc0011024) | (3<<8), 0xc0011024); // 2'b01 8bit, 2'b11 16bit word
NX_CONSOLE_Printf( "TIEOFFREG9[10:9](0xc0011024) set 2'b11 0x%08x\n", readl( 0xc0011024 ) );
// POR of EHCI PHY
writel(readl(0xc0011020) & ~(3<<7), 0xc0011020);
writel(readl(0xc0011020) | (1<<7), 0xc0011020);
NX_CONSOLE_Printf( "TIEOFFREG8[8:7](0xc0011020) set 2'b01 0x%08x\n", readl( 0xc0011020 ) );
// Wait clock of PHY - about 40 micro seconds
udelay(40); // 40us delay need.
#if defined( CONFIG_USB_HSIC_MODE )
NX_CONSOLE_Printf( "\n HSIC PHY Init!!!\n" );
udelay(10); // 10us delay need.
// word interface in HSIC PHY
writel(readl(0xc001102c) & ~(3<<12), 0xc001102c);
writel(readl(0xc001102c) | (3<<12), 0xc001102c); // 2'b01 8bit, 2'b11 16bit word
// NX_CONSOLE_Printf( "TIEOFFREG9[10:9](0xc001102c) set 2'b11 0x%08x\n", readl( 0xc001102c ) );
// POR of HSIC PHY
writel(readl(0xc0011028) & ~(3<<18), 0xc0011028);
writel(readl(0xc0011028) | (1<<18), 0xc0011028);
// NX_CONSOLE_Printf( "TIEOFFREG8[19:18](0xc0011028) set 2'b01 0x%08x\n", readl( 0xc0011028 ) );
// 5. Wait clock of PHY - about 40 micro seconds
//udelay(40); // 40us delay need.
udelay(400); // 40us delay need.
#endif
// Release phy free clock reset
writel(readl(0xc0011014) | (1<<20), 0xc0011014);
udelay(2);
#if defined( CONFIG_USB_EHCI_MODE )
// Release ehci utmi reset
writel(readl(0xc0011014) | (1<<21), 0xc0011014);
udelay(2);
NX_CONSOLE_Printf( "TIEOFFREG5[21:20](0xc0011014) set 2'b11 0x%08x\n", readl( 0xc0011014 ) );
#endif
#if defined( CONFIG_USB_HSIC_MODE )
// Release hsic utmi reset
writel(readl(0xc0011014) | (1<<22), 0xc0011014);
udelay(2);
#endif
//Release ahb reset of EHCI
writel(readl(0xc0011014) | (1<<17), 0xc0011014);
//Release ahb reset of OHCI
writel(readl(0xc0011014) | (1<<18), 0xc0011014);
//Release auxwell reset of EHCI, OHCI
writel(readl(0xc0011014) | (1<<19), 0xc0011014);
// set Base Address
NX_USB20HOST_SetBaseAddress( 0, (void*)NX_USB20HOST_GetPhysicalAddress(0) );
*hccr = ( struct ehci_hccr * )( NX_USB20HOST_GetBaseAddress(0) );
*hcor = ( struct ehci_hcor * )( NX_USB20HOST_GetBaseAddress(0) + 0x10 );
// NX_CONSOLE_Printf( "Set EHCI Base Address : hccr( 0x%08x ), hcor( 0x%08x )\n" , *hccr, *hcor );
return 0;
}
