static void _set_resc_clkgen_pre(struct nxp_resc *me, bool enable, bool sink_is_hdmi) { NX_DISPTOP_CLKGEN_SetBaseAddress(ResConv_CLKGEN, (U32)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(ResConv_CLKGEN))); NX_DISPTOP_CLKGEN_SetClockDivisorEnable(ResConv_CLKGEN, CFALSE); if (enable) { NX_DISPTOP_CLKGEN_SetClockPClkMode(ResConv_CLKGEN, NX_PCLKMODE_ALWAYS); if (sink_is_hdmi) { NX_DISPTOP_CLKGEN_SetClockSource(ResConv_CLKGEN, ResConv_ICLK, 4); // HDMI CLK NX_DISPTOP_CLKGEN_SetClockDivisor(ResConv_CLKGEN, ResConv_ICLK, 1); } else { /* TODO : select iclk by sink */ pr_err("%s: TODO ==> select iclk for not hdmi\n", __func__); } NX_DISPTOP_CLKGEN_SetClockSource(ResConv_CLKGEN, ResConv_CCLK, 2); // PLL2 NX_DISPTOP_CLKGEN_SetClockDivisor(ResConv_CLKGEN, ResConv_CCLK, 1); NX_DISPTOP_CLKGEN_SetClockDivisorEnable(ResConv_CLKGEN, CTRUE); NX_DISPTOP_CLKGEN_SetBaseAddress(LCDIF_CLKGEN, (U32)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(LCDIF_CLKGEN))); NX_DISPTOP_CLKGEN_SetClockDivisorEnable ( LCDIF_CLKGEN, CFALSE); NX_DISPTOP_CLKGEN_SetClockPClkMode ( LCDIF_CLKGEN, NX_PCLKMODE_ALWAYS ); NX_DISPTOP_CLKGEN_SetClockDivisorEnable ( LCDIF_CLKGEN, CFALSE ); NX_DISPTOP_CLKGEN_SetClockSource ( LCDIF_CLKGEN, 0, 4 ); NX_DISPTOP_CLKGEN_SetClockDivisor ( LCDIF_CLKGEN, 0, 1 ); NX_DISPTOP_CLKGEN_SetClockSource ( LCDIF_CLKGEN, 1, 7 ); NX_DISPTOP_CLKGEN_SetClockDivisor ( LCDIF_CLKGEN, 1, 1 ); NX_DISPTOP_CLKGEN_SetClockDivisorEnable ( LCDIF_CLKGEN, CTRUE); } else { NX_DISPTOP_CLKGEN_SetClockDivisorEnable ( LCDIF_CLKGEN, CFALSE); NX_DISPTOP_CLKGEN_SetClockDivisorEnable(ResConv_CLKGEN, CFALSE); } }
static void mipi_initialize(void) { int clkid = DISP_CLOCK_MIPI; int index = 0; NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3); NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3); if (! nxp_soc_peri_reset_status(NX_MIPI_GetResetNumber(index, NX_MIPI_RST))) { nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST)); nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I)); nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S)); nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M)); nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST)); nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I)); nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S)); nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M)); } /* BASE : CLKGEN, MIPI */ NX_DISPTOP_CLKGEN_SetBaseAddress(clkid, (U32)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(clkid))); NX_DISPTOP_CLKGEN_SetClockPClkMode(clkid, NX_PCLKMODE_ALWAYS); /* BASE : MIPI */ NX_MIPI_Initialize(); NX_MIPI_SetBaseAddress(0, IO_ADDRESS(NX_MIPI_GetPhysicalAddress(0))); NX_MIPI_OpenModule(0); }
static void lvds_initialize(void) { int clkid = DISP_CLOCK_LVDS; int i; /* BASE : CLKGEN, LVDS */ NX_DISPTOP_CLKGEN_SetBaseAddress(clkid, (void*)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(clkid))); NX_DISPTOP_CLKGEN_SetClockPClkMode(clkid, NX_PCLKMODE_ALWAYS); /* BASE : LVDS */ NX_LVDS_Initialize(); for (i = 0; NX_LVDS_GetNumberOfModule() > i; i++) NX_LVDS_SetBaseAddress(i, (void*)IO_ADDRESS(NX_LVDS_GetPhysicalAddress(i))); }
static void _set_hdmi_clk_27MHz(void) { NX_HDMI_SetBaseAddress(0, (void *)IO_ADDRESS(NX_HDMI_GetPhysicalAddress(0))); NX_TIEOFF_Initialize(); NX_TIEOFF_SetBaseAddress((void *)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress())); NX_TIEOFF_Set(TIEOFFINDEX_OF_DISPLAYTOP0_i_HDMI_PHY_REFCLK_SEL, 1); // HDMI PCLK Enable NX_DISPTOP_CLKGEN_SetBaseAddress(HDMI_CLKGEN, (void *)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(HDMI_CLKGEN))); NX_DISPTOP_CLKGEN_SetClockPClkMode(HDMI_CLKGEN, NX_PCLKMODE_ALWAYS); // Enter Reset NX_RSTCON_SetRST (NX_HDMI_GetResetNumber(0, i_nRST_PHY) , 0); NX_RSTCON_SetRST (NX_HDMI_GetResetNumber(0, i_nRST) , 0); // APB // Release Reset NX_RSTCON_SetRST (NX_HDMI_GetResetNumber(0, i_nRST_PHY) , 1); NX_RSTCON_SetRST (NX_HDMI_GetResetNumber(0, i_nRST) , 1); // APB NX_DISPTOP_CLKGEN_SetClockPClkMode (HDMI_CLKGEN, NX_PCLKMODE_ALWAYS); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (0<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (0<<7) ); /// MODE_SET_DONE : APB Set NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, (0<<4) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, (0<<4) ); ///CLK_SEL : REF OSC or INT_CLK NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, (1<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, (1<<7) ); // INT REFCLK : ³»ºÎÀÇ syscon¿¡¼ ¹Þ´Â clock NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, 0xD1 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, 0xD1 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg08, 0x22 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg08, 0x22 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg0C, 0x51 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg0C, 0x51 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg10, 0x40 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg10, 0x40 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg14, 0x8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg14, 0x8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg18, 0xFC ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg18, 0xFC ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg1C, 0xE0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg1C, 0xE0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg20, 0x98 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg20, 0x98 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, 0xE8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, 0xE8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg28, 0xCB ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg28, 0xCB ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg2C, 0xD8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg2C, 0xD8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg30, 0x45 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg30, 0x45 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg34, 0xA0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg34, 0xA0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg38, 0xAC ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg38, 0xAC ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg3C, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg3C, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg40, 0x6 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg40, 0x6 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg44, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg44, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg48, 0x9 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg48, 0x9 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg4C, 0x84 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg4C, 0x84 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg50, 0x5 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg50, 0x5 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg54, 0x22 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg54, 0x22 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg58, 0x24 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg58, 0x24 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg5C, 0x86 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg5C, 0x86 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg60, 0x54 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg60, 0x54 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg64, 0xE4 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg64, 0xE4 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg68, 0x24 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg68, 0x24 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg6C, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg6C, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg70, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg70, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg74, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg74, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg78, 0x1 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg78, 0x1 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (1<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (1<<7) ); /// MODE_SET_DONE : APB Set Done // wait phy ready { U32 Is_HDMI_PHY_READY = CFALSE; while(Is_HDMI_PHY_READY == CFALSE) { if(NX_HDMI_GetReg( 0, HDMI_LINK_PHY_STATUS_0 ) & 0x01) { Is_HDMI_PHY_READY = CTRUE; } } } }
static void _release_clk(int module) { NX_DISPTOP_CLKGEN_SetBaseAddress(HDMI_CLKGEN, (void *)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(HDMI_CLKGEN))); NX_DISPTOP_CLKGEN_SetClockDivisorEnable(HDMI_CLKGEN, CFALSE ); NX_DPC_SetClockDivisorEnable(module, CFALSE); }