static void cpu_base_init(void)
{
U32 tie_reg, val;
int i = 0;
NX_RSTCON_Initialize();
NX_RSTCON_SetBaseAddress((void*)IO_ADDRESS(NX_RSTCON_GetPhysicalAddress()));
NX_TIEOFF_Initialize();
NX_TIEOFF_SetBaseAddress((void*)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress()));
NX_GPIO_Initialize();
for (i = 0; NX_GPIO_GetNumberOfModule() > i; i++) {
NX_GPIO_SetBaseAddress(i, (void*)IO_ADDRESS(NX_GPIO_GetPhysicalAddress(i)));
NX_GPIO_OpenModule(i);
}
NX_ALIVE_Initialize();
NX_ALIVE_SetBaseAddress((void*)IO_ADDRESS(NX_ALIVE_GetPhysicalAddress()));
NX_ALIVE_OpenModule();
NX_CLKPWR_Initialize();
NX_CLKPWR_SetBaseAddress((void*)IO_ADDRESS(NX_CLKPWR_GetPhysicalAddress()));
NX_CLKPWR_OpenModule();
NX_ECID_Initialize();
NX_ECID_SetBaseAddress((void*)IO_ADDRESS(NX_ECID_GetPhysicalAddress()));
/*
* NOTE> ALIVE Power Gate must enable for RTC register access.
* must be clear wfi jump address
*/
NX_ALIVE_SetWriteEnable(CTRUE);
__raw_writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
/*
* NOTE> Control for ACP register access.
*/
tie_reg = (U32)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress());
val = __raw_readl(tie_reg + 0x70) & ~((3 << 30) | (3 << 10));
writel(val, (tie_reg + 0x70));
val = __raw_readl(tie_reg + 0x80) & ~(3 << 3);
writel(val, (tie_reg + 0x80));
}
static void cpu_base_init(void)
{
int i = 0;
NX_RSTCON_Initialize();
NX_RSTCON_SetBaseAddress((void*)IO_ADDRESS(NX_RSTCON_GetPhysicalAddress()));
NX_TIEOFF_Initialize();
NX_TIEOFF_SetBaseAddress((void*)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress()));
NX_CLKGEN_Initialize();
for (i = 0; NX_CLKGEN_GetNumberOfModule() > i; i++)
NX_CLKGEN_SetBaseAddress(i, (void*)IO_ADDRESS(NX_CLKGEN_GetPhysicalAddress(i)));
NX_GPIO_Initialize();
for (i = 0; NX_GPIO_GetNumberOfModule() > i; i++) {
NX_GPIO_SetBaseAddress(i, (void*)IO_ADDRESS(NX_GPIO_GetPhysicalAddress(i)));
NX_GPIO_OpenModule(i);
}
NX_ALIVE_Initialize();
NX_ALIVE_SetBaseAddress((void*)IO_ADDRESS(NX_ALIVE_GetPhysicalAddress()));
NX_ALIVE_OpenModule();
NX_CLKPWR_Initialize();
NX_CLKPWR_SetBaseAddress((void*)IO_ADDRESS(NX_CLKPWR_GetPhysicalAddress()));
NX_CLKPWR_OpenModule();
/*
* NOTE> ALIVE Power Gate must enable for RTC register access.
* must be clear wfi jump address
*/
NX_ALIVE_SetWriteEnable(CTRUE);
__raw_writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
// write 0xf0 on alive scratchpad reg for boot success check
NX_ALIVE_SetScratchReg(NX_ALIVE_GetScratchReg() | 0xF0);
NX_WDT_Initialize();
NX_WDT_SetBaseAddress(0, (void*)IO_ADDRESS(NX_WDT_GetPhysicalAddress(0)));
NX_WDT_OpenModule(0);
// watchdog disable
if (NX_WDT_GetEnable(0)) {
NX_WDT_SetEnable(0, CFALSE);
NX_WDT_SetResetEnable(0, CFALSE);
NX_WDT_ClearInterruptPending(0, NX_WDT_GetInterruptNumber(0));
}
}
static void cpu_base_init(void)
{
int i = 0;
NX_RSTCON_Initialize();
NX_RSTCON_SetBaseAddress((void*)IO_ADDRESS(NX_RSTCON_GetPhysicalAddress()));
NX_TIEOFF_Initialize();
NX_TIEOFF_SetBaseAddress((void*)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress()));
NX_GPIO_Initialize();
for (i = 0; NX_GPIO_GetNumberOfModule() > i; i++) {
NX_GPIO_SetBaseAddress(i, (void*)IO_ADDRESS(NX_GPIO_GetPhysicalAddress(i)));
NX_GPIO_OpenModule(i);
}
NX_ALIVE_Initialize();
NX_ALIVE_SetBaseAddress((void*)IO_ADDRESS(NX_ALIVE_GetPhysicalAddress()));
NX_ALIVE_OpenModule();
NX_CLKPWR_Initialize();
NX_CLKPWR_SetBaseAddress((void*)IO_ADDRESS(NX_CLKPWR_GetPhysicalAddress()));
NX_CLKPWR_OpenModule();
NX_ECID_Initialize();
NX_ECID_SetBaseAddress((void*)IO_ADDRESS(NX_ECID_GetPhysicalAddress()));
/*
* NOTE> ALIVE Power Gate must enable for RTC register access.
* must be clear wfi jump address
*/
NX_ALIVE_SetWriteEnable(CTRUE);
__raw_writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
/* clear cpu id register for second cores */
__raw_writel((-1UL), SCR_SMP_WAKE_CPU_ID);
}
static void cpu_base_init(void)
{
U32 tie_reg, val;
int i = 0;
NX_RSTCON_Initialize();
NX_RSTCON_SetBaseAddress((void*)IO_ADDRESS(NX_RSTCON_GetPhysicalAddress()));
NX_TIEOFF_Initialize();
NX_TIEOFF_SetBaseAddress((void*)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress()));
NX_CLKGEN_Initialize();
for (i = 0; NX_CLKGEN_GetNumberOfModule() > i; i++)
NX_CLKGEN_SetBaseAddress(i, (void*)IO_ADDRESS(NX_CLKGEN_GetPhysicalAddress(i)));
NX_GPIO_Initialize();
for (i = 0; NX_GPIO_GetNumberOfModule() > i; i++) {
NX_GPIO_SetBaseAddress(i, (void*)IO_ADDRESS(NX_GPIO_GetPhysicalAddress(i)));
NX_GPIO_OpenModule(i);
}
NX_ALIVE_Initialize();
NX_ALIVE_SetBaseAddress((void*)IO_ADDRESS(NX_ALIVE_GetPhysicalAddress()));
NX_ALIVE_OpenModule();
NX_CLKPWR_Initialize();
NX_CLKPWR_SetBaseAddress((void*)IO_ADDRESS(NX_CLKPWR_GetPhysicalAddress()));
NX_CLKPWR_OpenModule();
/*
* NOTE> ALIVE Power Gate must enable for RTC register access.
* must be clear wfi jump address
*/
NX_ALIVE_SetWriteEnable(CTRUE);
__raw_writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
/*
* NOTE> Control for ACP register access.
*/
tie_reg = (U32)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress());
val = __raw_readl(tie_reg + 0x70) & ~((3 << 30) | (3 << 10));
writel(val, (tie_reg + 0X70));
val = __raw_readl(tie_reg + 0x80) & ~(3 << 3);
writel(val, (tie_reg + 0x80));
/* add by cym 20150811 */
#ifdef CONFIG_MACH_S5P6818
/* end add */
// write 0xf0 on alive scratchpad reg for boot success check
NX_ALIVE_SetScratchReg(NX_ALIVE_GetScratchReg() | 0xF0);
NX_WDT_Initialize();
NX_WDT_SetBaseAddress(0, (void*)IO_ADDRESS(NX_WDT_GetPhysicalAddress(0)));
NX_WDT_OpenModule(0);
// watchdog disable
if (NX_WDT_GetEnable(0)) {
NX_WDT_SetEnable(0, CFALSE);
NX_WDT_SetResetEnable(0, CFALSE);
NX_WDT_ClearInterruptPending(0, NX_WDT_GetInterruptNumber(0));
}
/* add by cym 20150811 */
#endif
/* end add */
}
static void _set_hdmi_clk_27MHz(void)
{
NX_HDMI_SetBaseAddress(0, (void *)IO_ADDRESS(NX_HDMI_GetPhysicalAddress(0)));
NX_TIEOFF_Initialize();
NX_TIEOFF_SetBaseAddress((void *)IO_ADDRESS(NX_TIEOFF_GetPhysicalAddress()));
NX_TIEOFF_Set(TIEOFFINDEX_OF_DISPLAYTOP0_i_HDMI_PHY_REFCLK_SEL, 1);
// HDMI PCLK Enable
NX_DISPTOP_CLKGEN_SetBaseAddress(HDMI_CLKGEN, (void *)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(HDMI_CLKGEN)));
NX_DISPTOP_CLKGEN_SetClockPClkMode(HDMI_CLKGEN, NX_PCLKMODE_ALWAYS);
// Enter Reset
NX_RSTCON_SetRST (NX_HDMI_GetResetNumber(0, i_nRST_PHY) , 0);
NX_RSTCON_SetRST (NX_HDMI_GetResetNumber(0, i_nRST) , 0); // APB
// Release Reset
NX_RSTCON_SetRST (NX_HDMI_GetResetNumber(0, i_nRST_PHY) , 1);
NX_RSTCON_SetRST (NX_HDMI_GetResetNumber(0, i_nRST) , 1); // APB
NX_DISPTOP_CLKGEN_SetClockPClkMode (HDMI_CLKGEN, NX_PCLKMODE_ALWAYS);
NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (0<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (0<<7) ); /// MODE_SET_DONE : APB Set
NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, (0<<4) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, (0<<4) ); ///CLK_SEL : REF OSC or INT_CLK
NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, (1<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, (1<<7) ); // INT REFCLK : ³»ºÎÀÇ syscon¿¡¼ ¹Þ´Â clock
NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, 0xD1 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg04, 0xD1 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg08, 0x22 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg08, 0x22 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg0C, 0x51 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg0C, 0x51 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg10, 0x40 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg10, 0x40 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg14, 0x8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg14, 0x8 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg18, 0xFC ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg18, 0xFC );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg1C, 0xE0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg1C, 0xE0 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg20, 0x98 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg20, 0x98 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, 0xE8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg24, 0xE8 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg28, 0xCB ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg28, 0xCB );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg2C, 0xD8 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg2C, 0xD8 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg30, 0x45 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg30, 0x45 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg34, 0xA0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg34, 0xA0 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg38, 0xAC ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg38, 0xAC );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg3C, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg3C, 0x80 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg40, 0x6 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg40, 0x6 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg44, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg44, 0x80 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg48, 0x9 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg48, 0x9 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg4C, 0x84 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg4C, 0x84 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg50, 0x5 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg50, 0x5 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg54, 0x22 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg54, 0x22 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg58, 0x24 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg58, 0x24 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg5C, 0x86 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg5C, 0x86 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg60, 0x54 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg60, 0x54 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg64, 0xE4 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg64, 0xE4 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg68, 0x24 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg68, 0x24 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg6C, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg6C, 0x0 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg70, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg70, 0x0 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg74, 0x0 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg74, 0x0 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg78, 0x1 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg78, 0x1 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, 0x80 ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, 0x80 );
NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (1<<7) ); NX_HDMI_SetReg( 0, HDMI_PHY_Reg7C, (1<<7) ); /// MODE_SET_DONE : APB Set Done
// wait phy ready
{
U32 Is_HDMI_PHY_READY = CFALSE;
while(Is_HDMI_PHY_READY == CFALSE) {
if(NX_HDMI_GetReg( 0, HDMI_LINK_PHY_STATUS_0 ) & 0x01) {
Is_HDMI_PHY_READY = CTRUE;
}
}
}
}
