void
NvRmPrivGetSku( NvRmDeviceHandle rm )
{
NvError e;
NvRmChipId *id;
NvU8 *FuseVirt;
NvU32 reg;
#if NV_USE_FUSE_CLOCK_ENABLE
NvU8 *CarVirt = 0;
#endif
NV_ASSERT( rm );
id = &rm->ChipId;
#if NV_USE_FUSE_CLOCK_ENABLE
// Enable fuse clock
e = NvRmPhysicalMemMap(0x60006000, 0x1000, NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached, (void **)&CarVirt);
if (e == NvSuccess)
{
reg = NV_READ32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
reg |= 0x80;
NV_WRITE32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, reg);
}
#endif
/* Read the fuse only on real silicon, as it was not gauranteed to be
* preset on the eluation/simulation platforms.
*/
e = NvRmPhysicalMemMap(0x7000f800, 0x400, NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached, (void **)&FuseVirt);
if (e == NvSuccess)
{
// Read the SKU from the fuse module.
reg = NV_READ32( FuseVirt + FUSE_SKU_INFO_0 );
id->SKU = (NvU16)reg;
NvRmPhysicalMemUnmap(FuseVirt, 0x400);
#if NV_USE_FUSE_CLOCK_ENABLE
// Disable fuse clock
if (CarVirt)
{
reg = NV_READ32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
reg &= ~0x80;
NV_WRITE32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, reg);
NvRmPhysicalMemUnmap(CarVirt, 0x1000);
}
#endif
} else
{
NV_ASSERT(!"Cannot map the FUSE aperture to get the SKU");
id->SKU = 0;
}
}
void
NvRmPrivUnmapApertures( NvRmDeviceHandle rm )
{
NvRmModuleTable *tbl;
NvRmModuleInstance *inst;
NvRmModule *mod;
NvU32 devid;
NvU32 i;
NV_ASSERT( rm );
/* loop over the instance list and unmap everything */
tbl = &rm->ModuleTable;
mod = tbl->Modules;
for( i = 0; i < NvRmPrivModuleID_Num; i++ )
{
if( mod[i].Index == NVRM_MODULE_INVALID )
{
continue;
}
/* map all of the device instances */
inst = tbl->ModInst + mod[i].Index;
devid = inst->DeviceId;
while( devid == inst->DeviceId )
{
NvRmPhysicalMemUnmap( inst->VirtAddr, inst->Length );
inst++;
}
}
}
void NvRmPwmClose(NvRmPwmHandle hPwm)
{
NvU32 i;
if (!hPwm)
return;
NV_ASSERT(hPwm->RefCount);
NvOsMutexLock(s_hPwmMutex);
hPwm->RefCount--;
if (hPwm->RefCount == 0)
{
// Unmap the pwm register virtual address space
for (i = 0; i < NvRmPwmOutputId_Num-2; i++)
{
NvRmPhysicalMemUnmap((void*)s_hPwm->VirtualAddress[i],
s_hPwm->PwmBankSize);
}
// Unmap the pmc register virtual address space
NvRmPhysicalMemUnmap(
(void*)s_hPwm->VirtualAddress[NvRmPwmOutputId_Num-2],
s_hPwm->PmcBankSize);
if (s_IsPwmFirstConfig)
{
// Disable power
PwmPowerConfigure(hPwm, NV_FALSE);
// Unregister with RM power
NvRmPowerUnRegister(hPwm->RmDeviceHandle, s_PwmPowerID);
// Tri-state the pin-mux pins
NV_ASSERT_SUCCESS(NvRmSetModuleTristate(hPwm->RmDeviceHandle,
NVRM_MODULE_ID(NvRmModuleID_Pwm, 0), NV_TRUE));
s_IsPwmFirstConfig = NV_FALSE;
}
NvOsFree(s_hPwm);
s_hPwm = NULL;
}
NvOsMutexUnlock(s_hPwmMutex);
}
void
NvRmPrivReadChipId( NvRmDeviceHandle rm )
{
#if (NVCPU_IS_X86 && NVOS_IS_WINDOWS)
NvRmChipId *id;
NV_ASSERT( rm );
id = &rm->ChipId;
id->Family = NvRmChipFamily_HandheldSoc;
id->Id = 0x15;
id->Major = 0x0;
id->Minor = 0x0;
id->SKU = 0x0;
id->Netlist = 0x0;
id->Patch = 0x0;
#else
NvU32 reg;
NvRmChipId *id;
NvU32 fam;
char *s;
NvU8 *VirtAddr;
NvError e;
NV_ASSERT( rm );
id = &rm->ChipId;
/* Hard coding the address of the chip ID address space, as we haven't yet
* parsed the relocation table.
*/
e = NvRmPhysicalMemMap(0x70000000, 0x1000, NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached, (void **)&VirtAddr);
if (e != NvSuccess)
{
NV_DEBUG_PRINTF(("APB misc aperture map failure\n"));
return;
}
/* chip id is in the misc aperture */
reg = NV_READ32( VirtAddr + APB_MISC_GP_HIDREV_0 );
id->Id = (NvU16)NV_DRF_VAL( APB_MISC_GP, HIDREV, CHIPID, reg );
id->Major = (NvU8)NV_DRF_VAL( APB_MISC_GP, HIDREV, MAJORREV, reg );
id->Minor = (NvU8)NV_DRF_VAL( APB_MISC_GP, HIDREV, MINORREV, reg );
fam = NV_DRF_VAL( APB_MISC_GP, HIDREV, HIDFAM, reg );
switch( fam ) {
case APB_MISC_GP_HIDREV_0_HIDFAM_GPU:
id->Family = NvRmChipFamily_Gpu;
s = "GPU";
break;
case APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD:
id->Family = NvRmChipFamily_Handheld;
s = "Handheld";
break;
case APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS:
id->Family = NvRmChipFamily_BrChips;
s = "BrChips";
break;
case APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH:
id->Family = NvRmChipFamily_Crush;
s = "Crush";
break;
case APB_MISC_GP_HIDREV_0_HIDFAM_MCP:
id->Family = NvRmChipFamily_Mcp;
s = "MCP";
break;
case APB_MISC_GP_HIDREV_0_HIDFAM_CK:
id->Family = NvRmChipFamily_Ck;
s = "Ck";
break;
case APB_MISC_GP_HIDREV_0_HIDFAM_VAIO:
id->Family = NvRmChipFamily_Vaio;
s = "Vaio";
break;
case APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC:
id->Family = NvRmChipFamily_HandheldSoc;
s = "Handheld SOC";
break;
default:
NV_ASSERT( !"bad chip family" );
NvRmPhysicalMemUnmap(VirtAddr, 0x1000);
return;
}
reg = NV_READ32( VirtAddr + APB_MISC_GP_EMU_REVID_0 );
id->Netlist = (NvU16)NV_DRF_VAL( APB_MISC_GP, EMU_REVID, NETLIST, reg );
id->Patch = (NvU16)NV_DRF_VAL( APB_MISC_GP, EMU_REVID, PATCH, reg );
if( id->Major == 0 )
{
char *emu;
if( id->Netlist == 0 )
{
NvOsDebugPrintf( "Simulation Chip: 0x%x\n", id->Id );
}
else
{
if( id->Minor == 0 )
{
emu = "QuickTurn";
}
else
{
emu = "FPGA";
}
NvOsDebugPrintf( "Emulation (%s) Chip: 0x%x Netlist: 0x%x "
"Patch: 0x%x\n", emu, id->Id, id->Netlist, id->Patch );
}
}
else
{
// on real silicon
NvRmPrivGetSku( rm );
NvOsDebugPrintf( "Chip Id: 0x%x (%s) Major: 0x%x Minor: 0x%x "
"SKU: 0x%x\n", id->Id, s, id->Major, id->Minor, id->SKU );
}
// add a sanity check here, so that if we think we are on sim, but don't
// detect a sim/quickturn netlist bail out with an error
if ( NvRmIsSimulation() && id->Major != 0 )
{
// this should all get optimized away in release builds because the
// above will get evaluated to if ( 0 )
NV_ASSERT(!"invalid major version number for simulation");
}
NvRmPhysicalMemUnmap(VirtAddr, 0x1000);
#endif
}
void
NvDdkUsbPhyClose(
NvDdkUsbPhyHandle hUsbPhy)
{
if (!hUsbPhy)
return;
NvOsMutexLock(s_UsbPhyMutex);
if (!hUsbPhy->RefCount)
{
NvOsMutexUnlock(s_UsbPhyMutex);
return;
}
--hUsbPhy->RefCount;
if (hUsbPhy->RefCount)
{
NvOsMutexUnlock(s_UsbPhyMutex);
return;
}
NvRmSetModuleTristate(
hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
NV_TRUE);
NvOsMutexLock(hUsbPhy->ThreadSafetyMutex);
if (hUsbPhy->RmPowerClientId)
{
if (hUsbPhy->IsPhyPoweredUp)
{
NV_ASSERT_SUCCESS(
NvRmPowerModuleClockControl(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
hUsbPhy->RmPowerClientId,
NV_FALSE));
//NvOsDebugPrintf("NvDdkUsbPhyClose::VOLTAGE OFF\n");
NV_ASSERT_SUCCESS(
NvRmPowerVoltageControl(hUsbPhy->hRmDevice,
NVRM_MODULE_ID(NvRmModuleID_Usb2Otg, hUsbPhy->Instance),
hUsbPhy->RmPowerClientId,
NvRmVoltsOff, NvRmVoltsOff,
NULL, 0, NULL));
hUsbPhy->IsPhyPoweredUp = NV_FALSE;
}
// Unregister driver from Power Manager
NvRmPowerUnRegister(hUsbPhy->hRmDevice, hUsbPhy->RmPowerClientId);
NvOsSemaphoreDestroy(hUsbPhy->hPwrEventSem);
}
NvOsMutexUnlock(hUsbPhy->ThreadSafetyMutex);
NvOsMutexDestroy(hUsbPhy->ThreadSafetyMutex);
if (hUsbPhy->CloseHwInterface)
{
hUsbPhy->CloseHwInterface(hUsbPhy);
}
if ((hUsbPhy->pProperty->UsbMode == NvOdmUsbModeType_Host) ||
(hUsbPhy->pProperty->UsbMode == NvOdmUsbModeType_OTG))
{
UsbPrivEnableVbus(hUsbPhy, NV_FALSE);
}
NvOdmEnableUsbPhyPowerRail(NV_FALSE);
NvRmPhysicalMemUnmap(
(void*)hUsbPhy->UsbVirAdr, hUsbPhy->UsbBankSize);
NvRmPhysicalMemUnmap(
(void*)hUsbPhy->MiscVirAdr, hUsbPhy->MiscBankSize);
NvOsMemset(hUsbPhy, 0, sizeof(NvDdkUsbPhy));
NvOsMutexUnlock(s_UsbPhyMutex);
}
