void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct adapter *adapter = dm_odm->Adapter; if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV)) return; if (!dm_odm->bLinked) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n")); if (dm_fat_tbl->bBecomeLinked) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n")); PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* RegC50[7]=1'b1 enable HW AntDiv */ PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0); /* Enable CCK AntDiv */ if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */ dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; } return; } else { if (!dm_fat_tbl->bBecomeLinked) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n")); /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */ PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1); /* Enable CCK AntDiv */ if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */ dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; } } if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)) odm_HWAntDiv(dm_odm); }
/* check if edca turbo is disabled */ boolean odm_is_edca_turbo_disable( void *p_dm_void ) { struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; struct _ADAPTER *adapter = p_dm_odm->adapter; PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; u32 iot_peer = p_mgnt_info->iot_peer; if (p_dm_odm->is_bt_disable_edca_turbo) { ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n")); return true; } if ((!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO)) || (p_dm_odm->wifi_test & RT_WIFI_LOGO) || (iot_peer >= HT_IOT_PEER_MAX)) { ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable\n")); return true; } /* 1. We do not turn on EDCA turbo mode for some AP that has IOT issue */ /* 2. User may disable EDCA Turbo mode with OID settings. */ if (p_mgnt_info->iot_action & HT_IOT_ACT_DISABLE_EDCA_TURBO) { ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("iot_action:EdcaTurboDisable\n")); return true; } return false; }
void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct adapter *adapter = dm_odm->Adapter; u32 DefaultAnt, OptionalAnt; if (dm_fat_tbl->RxIdleAnt != Ant) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n")); if (Ant == MAIN_ANT) { DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; } else { DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; } if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */ PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */ PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT14|BIT13|BIT12, DefaultAnt); /* Default TX */ PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT6|BIT7, DefaultAnt); /* Resp Tx */ } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */ PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */ } } dm_fat_tbl->RxIdleAnt = Ant; ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); pr_info("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); }
static void odm_HWAntDiv(struct odm_dm_struct *dm_odm) { u32 i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI; u32 Main_RSSI, Aux_RSSI; u8 RxIdleAnt = 0, TargetAnt = 7; struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable; struct sta_info *pEntry; for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { pEntry = dm_odm->pODM_StaInfo[i]; if (IS_STA_VALID(pEntry)) { /* 2 Caculate RSSI per Antenna */ Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i]/dm_fat_tbl->MainAnt_Cnt[i]) : 0; Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0; TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT; ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, dm_fat_tbl->MainAnt_Sum[i], dm_fat_tbl->MainAnt_Cnt[i])); ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n", i, dm_fat_tbl->AuxAnt_Sum[i], dm_fat_tbl->AuxAnt_Cnt[i])); ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI)); /* 2 Select MaxRSSI for DIG */ LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI; if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) AntDivMaxRSSI = LocalMaxRSSI; if (LocalMaxRSSI > MaxRSSI) MaxRSSI = LocalMaxRSSI; /* 2 Select RX Idle Antenna */ if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0)) Main_RSSI = Aux_RSSI; else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0)) Aux_RSSI = Main_RSSI; LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI; if (LocalMinRSSI < MinRSSI) { MinRSSI = LocalMinRSSI; RxIdleAnt = TargetAnt; } /* 2 Select TRX Antenna */ if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i); } dm_fat_tbl->MainAnt_Sum[i] = 0; dm_fat_tbl->AuxAnt_Sum[i] = 0; dm_fat_tbl->MainAnt_Cnt[i] = 0; dm_fat_tbl->AuxAnt_Cnt[i] = 0; } /* 2 Set RX Idle Antenna */ ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt); pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; pDM_DigTable->RSSI_max = MaxRSSI; }
VOID ODM_CfoTrackingReset( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm); pCfoTrack->bAdjust = TRUE; if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap) { odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap - 1); ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); } else if (pCfoTrack->CrystalCap < pCfoTrack->DefXCap) { odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap + 1); ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); } #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) odm_SetATCStatus(pDM_Odm, TRUE); #endif }
/*----------------------------------------------------------------------------- * Function: odm_RefreshRateAdaptiveMask() * * Overview: Update rate table mask according to rssi * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 05/27/2009 hpfan Create Version 0. * *---------------------------------------------------------------------------*/ VOID odm_RefreshRateAdaptiveMask( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask()---------->\n")); if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask(): Return cos not supported\n")); return; } // // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate // at the same time. In the stage2/3, we need to prive universal interface and merge all // HW dynamic mechanism. // switch (pDM_Odm->SupportPlatform) { case ODM_WIN: odm_RefreshRateAdaptiveMaskMP(pDM_Odm); break; case ODM_CE: odm_RefreshRateAdaptiveMaskCE(pDM_Odm); break; case ODM_AP: case ODM_ADSL: odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); break; } }
void odm_edca_turbo_check(void *dm_void) { /* For AP/ADSL use struct rtl8192cd_priv* */ /* For CE/NIC use struct void* */ /* 2011/09/29 MH In HW integration first stage, we provide 4 different * handle to operate at the same time. * In the stage2/3, we need to prive universal interface and merge all * HW dynamic mechanism. */ struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void; ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "%s========================>\n", __func__); if (!(dm->support_ability & ODM_MAC_EDCA_TURBO)) return; switch (dm->support_platform) { case ODM_WIN: break; case ODM_CE: odm_edca_turbo_check_ce(dm); break; } ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "<========================%s\n", __func__); } /* odm_CheckEdcaTurbo */
VOID ODM_AntennaDiversityInit_88E( IN PDM_ODM_T pDM_Odm ) { /* //2012.03.27 LukeLee: For temp use, should be removed later //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; //{ PADAPTER Adapter = pDM_Odm->Adapter; HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); //pHalData->AntDivCfg = 1; //} */ if(pDM_Odm->SupportICType != ODM_RTL8188E) return; //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n", // pDM_Odm->AntDivType, pHalData->AntDivCfg)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"TRUE":"FALSE"))); if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) odm_RX_HWAntDivInit(pDM_Odm); else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) odm_TRX_HWAntDivInit(pDM_Odm); else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) odm_FastAntTrainingInit(pDM_Odm); }
void odm_edca_choose_traffic_idx( void *p_dm_void, u64 cur_tx_bytes, u64 cur_rx_bytes, boolean is_bias_on_rx, boolean *p_is_cur_rdl_state ) { struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; if (is_bias_on_rx) { if (cur_tx_bytes > (cur_rx_bytes * 4)) { *p_is_cur_rdl_state = false; ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Uplink Traffic\n ")); } else { *p_is_cur_rdl_state = true; ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n")); } } else { if (cur_rx_bytes > (cur_tx_bytes * 4)) { *p_is_cur_rdl_state = true; ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Downlink Traffic\n")); } else { *p_is_cur_rdl_state = false; ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n")); } } return ; }
VOID odm_SetCrystalCap( IN PVOID pDM_VOID, IN u1Byte CrystalCap ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); BOOLEAN bEEPROMCheck; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) PADAPTER Adapter = pDM_Odm->Adapter; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); bEEPROMCheck = (pHalData->EEPROMVersion >= 0x01)?TRUE:FALSE; #else bEEPROMCheck = TRUE; #endif if(pCfoTrack->CrystalCap == CrystalCap) return; pCfoTrack->CrystalCap = CrystalCap; if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) { /* write 0x24[22:17] = 0x24[16:11] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6))); } else if (pDM_Odm->SupportICType & ODM_RTL8812) { /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6))); } else if (((pDM_Odm->SupportICType & ODM_RTL8723A) && bEEPROMCheck) || (pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) { /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6))); } else if (pDM_Odm->SupportICType & ODM_RTL8821B) { /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7E000000, CrystalCap); ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7E, CrystalCap); } else if (pDM_Odm->SupportICType & ODM_RTL8814A) { /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6))); } else if (pDM_Odm->SupportICType & ODM_RTL8822B) { /* write 0x24[30:25] = 0x28[6:1] = CrystalCap */ CrystalCap = CrystalCap & 0x3F; ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap); ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap); } else { ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n")); ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6))); } ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap)); #endif }
VOID _LOK_One_Shot( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; u1Byte Path = 0, delay_count = 0, ii; BOOLEAN LOK_notready = FALSE; u4Byte LOK_temp1 = 0, LOK_temp2 = 0; ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("============ LOK ============\n")); for(Path =0; Path <=3; Path++){ ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("==========S%d LOK ==========\n", Path)); ODM_SetBBReg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path); // ADC Clock source ODM_Write4Byte(pDM_Odm, 0x1b00, (0xf8000001|(1<<(4+Path)))); // LOK: CMD ID = 0 {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081} ODM_delay_ms(LOK_delay); delay_count = 0; LOK_notready = TRUE; while(LOK_notready){ LOK_notready = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b00, BIT(0)); ODM_delay_ms(1); delay_count++; if(delay_count >= 10){ ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("S%d LOK timeout!!!\n", Path)); _IQK_ResetNCTL_8814A(pDM_Odm); break; } } ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("S%d ==> delay_count = 0x%d\n", Path, delay_count)); if(!LOK_notready){ ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1)); ODM_Write4Byte(pDM_Odm, 0x1bd4, 0x003f0001); LOK_temp2 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x003e0000)+0x10)&0x1f; LOK_temp1 = (ODM_GetBBReg(pDM_Odm, 0x1bfc, 0x0000003e)+0x10)&0x1f; for(ii = 1; ii<5; ii++){ LOK_temp1 = LOK_temp1 + ((LOK_temp1 & BIT(4-ii))<<(ii*2)); LOK_temp2 = LOK_temp2 + ((LOK_temp2 & BIT(4-ii))<<(ii*2)); } ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("LOK_temp1 = 0x%x, LOK_temp2 = 0x%x\n", LOK_temp1>>4, LOK_temp2>>4)); ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0x07c00, LOK_temp1>>4); ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x8, 0xf8000, LOK_temp2>>4); ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("==>S%d fill LOK\n", Path)); } else{
void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->AntDivType=%d\n", dm_odm->AntDivType)); ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->bIsMPChip=%s\n", (dm_odm->bIsMPChip ? "true" : "false"))); if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) odm_RX_HWAntDivInit(dm_odm); else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) odm_TRX_HWAntDivInit(dm_odm); else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV) odm_FastAntTrainingInit(dm_odm); }
VOID ODM_CfoTrackingInit( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm); pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm); pCfoTrack->bAdjust = TRUE; ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========> \n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x \n",pCfoTrack->bATCStatus, pCfoTrack->DefXCap)); }
void ODM_CfoTrackingInit( IN void * pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack; pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm); pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm); pCfoTrack->bAdjust = true; ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========> \n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x \n",pCfoTrack->bATCStatus, pCfoTrack->DefXCap)); }
VOID HalTxbf8814A_Status( IN PVOID pDM_VOID, IN u1Byte Idx ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; u2Byte BeamCtrlVal, tmpVal; u4Byte BeamCtrlReg; PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; RT_BEAMFORMEE_ENTRY BeamformEntry; if (Idx < BEAMFORMEE_ENTRY_NUM) BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx]; else return; if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) BeamCtrlVal = BeamformEntry.MacId; else BeamCtrlVal = BeamformEntry.P_AID; ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, BeamformEntry.BeamformEntryState)); if (Idx == 0) BeamCtrlReg = REG_TXBF_CTRL_8814A; else { BeamCtrlReg = REG_TXBF_CTRL_8814A + 2; BeamCtrlVal |= BIT12 | BIT14 | BIT15; } if (BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) BeamCtrlVal |= BIT9; else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) BeamCtrlVal |= (BIT9 | BIT10); else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) BeamCtrlVal |= (BIT9 | BIT10 | BIT11); } else { ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); } ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); /*disable NDP packet use beamforming */ tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8814A); ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, tmpVal | BIT15); }
void odm_ConfigBB_PHY_REG_PG_8188E( PDM_ODM_T pDM_Odm, u4Byte Addr, u4Byte Bitmask, u4Byte Data ) { if (Addr == 0xfe){ ODM_sleep_ms(50); } else if (Addr == 0xfd){ ODM_delay_ms(5); } else if (Addr == 0xfc){ ODM_delay_ms(1); } else if (Addr == 0xfb){ ODM_delay_us(50); } else if (Addr == 0xfa){ ODM_delay_us(5); } else if (Addr == 0xf9){ ODM_delay_us(1); } else{ ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data); } }
void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) { if (Addr == 0xfe) { ODM_sleep_ms(50); } else if (Addr == 0xfd) { ODM_delay_ms(5); } else if (Addr == 0xfc) { ODM_delay_ms(1); } else if (Addr == 0xfb) { ODM_delay_us(50); } else if (Addr == 0xfa) { ODM_delay_us(5); } else if (Addr == 0xf9) { ODM_delay_us(1); } else { if (Addr == 0xa24) pDM_Odm->RFCalibrateInfo.RegA24 = Data; ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); /* Add 1us delay between BB/RF register setting. */ ODM_delay_us(1); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); } }
VOID halComTxbf_RateWorkItemCallback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) IN PADAPTER Adapter #else IN PVOID pDM_VOID #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; #else PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; #endif PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; u1Byte BW = pTxbfInfo->BW; u1Byte Rate = pTxbfInfo->Rate; ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); if (pDM_Odm->SupportICType & ODM_RTL8812) HalTxbf8812A_setNDPArate(pDM_Odm, BW, Rate); else if (pDM_Odm->SupportICType & ODM_RTL8192E) HalTxbf8192E_setNDPArate(pDM_Odm, BW, Rate); else if (pDM_Odm->SupportICType & ODM_RTL8814A) HalTxbf8814A_setNDPArate(pDM_Odm, BW, Rate); }
// // Description: According to initial gain value to determine to enable or disable EDCCA. // // Suggested by SD3 Wilson. Added by tynli. 2011.11.25. // VOID Phydm_DynamicEDCCA( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PADAPTER pAdapter = pDM_Odm->Adapter; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u1Byte RegC50, RegC58; BOOLEAN bEDCCAenable = FALSE; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) BOOLEAN bFwCurrentInPSMode=FALSE; pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode)); // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14. if(bFwCurrentInPSMode) return; #endif // // 2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA. // 2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop // to send beacon in noisy environment or platform. // if(ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter))) //if(ACTING_AS_AP(pAdapter)) { ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n")); Phydm_DisableEDCCA(pDM_Odm); if(pHalData->bPreEdccaEnable) Phydm_DisableEDCCA(pDM_Odm); pHalData->bPreEdccaEnable = FALSE; return; } RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0); if((RegC50 > 0x28 && RegC58 > 0x28) || ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28)) { if(!pHalData->bPreEdccaEnable) { Phydm_EnableEDCCA(pDM_Odm); pHalData->bPreEdccaEnable = TRUE; } } else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25)) { if(pHalData->bPreEdccaEnable) { Phydm_DisableEDCCA(pDM_Odm); pHalData->bPreEdccaEnable = FALSE; } } }
VOID ODM_ReleaseTimer( IN PDM_ODM_T pDM_Odm, IN PRT_TIMER pTimer ) { #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) #elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) PADAPTER Adapter = pDM_Odm->Adapter; // <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. // Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. if (pTimer == 0) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n")); return; } PlatformReleaseTimer(Adapter, pTimer); #endif }
VOID halComTxbf_StatusWorkItemCallback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) IN PADAPTER Adapter #else IN PVOID pDM_VOID #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; #else PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; #endif PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; u1Byte Idx = pTxbfInfo->TXBFIdx; ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) HalTxbfJaguar_Status(pDM_Odm, Idx); else if (pDM_Odm->SupportICType & ODM_RTL8192E) HalTxbf8192E_Status(pDM_Odm, Idx); else if (pDM_Odm->SupportICType & ODM_RTL8814A) HalTxbf8814A_Status(pDM_Odm, Idx); else if (pDM_Odm->SupportICType & ODM_RTL8821B) HalTxbf8821B_Status(pDM_Odm, Idx); else if (pDM_Odm->SupportICType & ODM_RTL8822B) HalTxbf8822B_Status(pDM_Odm, Idx); }
void ODM_ReadAndConfig_MP_8192E_TXPWR_LMT( IN PDM_ODM_T pDM_Odm ) { u4Byte i = 0; u4Byte ArrayLen = sizeof(Array_MP_8192E_TXPWR_LMT)/sizeof(pu1Byte); pu1Byte *Array = Array_MP_8192E_TXPWR_LMT; ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8192E_TXPWR_LMT\n")); for (i = 0; i < ArrayLen; i += 7 ) { pu1Byte regulation = Array[i]; pu1Byte band = Array[i+1]; pu1Byte bandwidth = Array[i+2]; pu1Byte rate = Array[i+3]; pu1Byte rfPath = Array[i+4]; pu1Byte chnl = Array[i+5]; pu1Byte val = Array[i+6]; odm_ConfigBB_TXPWR_LMT_8192E(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); } }
void ODM_ReadAndConfig_MP_8192E_TxPowerTrack_USB( IN PDM_ODM_T pDM_Odm ) { PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_MP_8192E\n")); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8192E, DELTA_SWINGIDX_SIZE*3); }
VOID HalTxbf8192E_Leave( IN PVOID pDM_VOID, IN u1Byte Idx ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; halTxbf8192E_RfMode(pDM_Odm, pBeamInfo); /* Clear P_AID of Beamformee * Clear MAC addresss of Beamformer * Clear Associated Bfmee Sel */ if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xC8); if (Idx == 0) { ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, 0); ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); } else { ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2) & 0xF000); ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); } ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d\n", __func__, Idx)); }
void phydm_txcurrentcalibration(struct phy_dm_struct *dm) { u8 efuse0x3D8, efuse0x3D7; u32 orig_rf0x18_path_a = 0, orig_rf0x18_path_b = 0; /* save original 0x18 value */ orig_rf0x18_path_a = odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xFFFFF); orig_rf0x18_path_b = odm_get_rf_reg(dm, ODM_RF_PATH_B, 0x18, 0xFFFFF); /* define efuse content */ efuse0x3D8 = dm->efuse0x3d8; efuse0x3D7 = dm->efuse0x3d7; /* check efuse content to judge whether need to calibration or not */ if (efuse0x3D7 == 0xFF) { ODM_RT_TRACE( dm, ODM_COMP_COMMON, "efuse content 0x3D7 == 0xFF, No need to do TxA cali\n"); return; } /* write RF register for calibration */ _txa_bias_cali_4_each_path(dm, ODM_RF_PATH_A, efuse0x3D7); _txa_bias_cali_4_each_path(dm, ODM_RF_PATH_B, efuse0x3D8); /* restore original 0x18 value */ odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xFFFFF, orig_rf0x18_path_a); odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x18, 0xFFFFF, orig_rf0x18_path_b); }
u1Byte halTxbf8814A_GetNrx( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; u1Byte Nrx = 0; if (pDM_Odm->RFType == ODM_4T4R) Nrx = 3; else if (pDM_Odm->RFType == ODM_3T3R) Nrx = 2; else if (pDM_Odm->RFType == ODM_2T2R) Nrx = 1; else if (pDM_Odm->RFType == ODM_2T3R) Nrx = 2; else if (pDM_Odm->RFType == ODM_2T4R) Nrx = 3; else if (pDM_Odm->RFType == ODM_1T1R) Nrx = 0; else if (pDM_Odm->RFType == ODM_1T2R) Nrx = 1; else Nrx = 0; ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Nrx = %d\n", __func__, Nrx)); return Nrx; }
void odm_ConfigBB_PHY_8812A( IN PDM_ODM_T pDM_Odm, IN u4Byte Addr, IN u4Byte Bitmask, IN u4Byte Data ) { if (Addr == 0xfe) { #ifdef CONFIG_LONG_DELAY_ISSUE ODM_sleep_ms(50); #else ODM_delay_ms(50); #endif } else if (Addr == 0xfd) { ODM_delay_ms(5); } else if (Addr == 0xfc) { ODM_delay_ms(1); } else if (Addr == 0xfb) { ODM_delay_us(50); } else if (Addr == 0xfa) { ODM_delay_us(5); } else if (Addr == 0xf9) { ODM_delay_us(1); } else { ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); // Add 1us delay between BB/RF register setting. ODM_delay_us(1); } ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); }
static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; u32 value32; if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */ PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* 1:CG, 0:CS */ return; } ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n")); /* MAC Setting */ value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ /* Pin Settings */ PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */ PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ /* OFDM Settings */ PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); /* CCK Settings */ PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */ PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */ }
void odm_ConfigBB_PHY_REG_PG_8812A( IN PDM_ODM_T pDM_Odm, IN u4Byte Band, IN u4Byte RfPath, IN u4Byte TxNum, IN u4Byte Addr, IN u4Byte Bitmask, IN u4Byte Data ) { if (Addr == 0xfe || Addr == 0xffe) { #ifdef CONFIG_LONG_DELAY_ISSUE ODM_sleep_ms(50); #else ODM_delay_ms(50); #endif } else { #if !(DM_ODM_SUPPORT_TYPE&ODM_AP) PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); #endif } ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); }
u1Byte halTxbf8814A_GetNtx( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; u1Byte Ntx = 0; #if DEV_BUS_TYPE == RT_USB_INTERFACE if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { if (*pDM_Odm->HubUsbMode == 2) {/*USB3.0*/ if (pDM_Odm->RFType == ODM_4T4R) Ntx = 3; else if (pDM_Odm->RFType == ODM_3T3R) Ntx = 2; else Ntx = 1; } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ Ntx = 1; else Ntx = 1; } else #endif { if (pDM_Odm->RFType == ODM_4T4R) Ntx = 3; else if (pDM_Odm->RFType == ODM_3T3R) Ntx = 2; else Ntx = 1; } ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Ntx = %d\n", __func__, Ntx)); return Ntx; }