/* * Stop clock to the card */ static void omap_mmc_stop_clock(struct mmc_omap_host *host) { OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); }
/* * Send init stream sequence to card * before sending IDLE command */ static void send_init_stream(struct omap_hsmmc_host *host) { int reg = 0; unsigned long timeout; if (host->protect_card) return; disable_irq(host->irq); OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((reg != CC) && time_before(jiffies, timeout)) reg = OMAP_HSMMC_READ(host->base, STAT) & CC; OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); OMAP_HSMMC_READ(host->base, STAT); enable_irq(host->irq); }
/* * Work Item to notify the core about card insertion/removal */ static void mmc_omap_detect(struct work_struct *work) { u16 vdd = 0; struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, mmc_carddetect_work); mmc_clk_try_enable(host); sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); if (host->carddetect) { if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) { /* * Set the VDD back to 3V when the card is removed * before the set_ios fn turns off the power. */ vdd = fls(host->mmc->ocr_avail) - 1; if (omap_mmc_switch_opcond(host, vdd) != 0) host->mmc->ios.vdd = vdd; } /* 1,5 sec is a lot, but 1,5 sec is safe... */ mmc_detect_change(host->mmc, (3 * HZ)/2); } else { OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | SRD); while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ; mmc_detect_change(host->mmc, (HZ * 50) / 1000); } }
static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) { u32 hctl, capa, value; /* Only MMC1 supports 3.0V */ if (host->id == OMAP_MMC1_DEVID) { hctl = SDVS30; capa = VS30 | VS18; } else { hctl = SDVS18; capa = VS18; } value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); value = OMAP_HSMMC_READ(host->base, CAPA); OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); /* Set the controller to AUTO IDLE mode */ value = OMAP_HSMMC_READ(host->base, SYSCONFIG); OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); /* Set SD bus power bit */ set_sd_bus_power(host); }
/* * Switch MMC interface voltage ... only relevant for MMC1. * * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. * The MMC2 transceiver controls are used instead of DAT4..DAT7. * Some chips, like eMMC ones, use internal transceivers. */ static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) { u32 reg_val = 0; int ret; /* Disable the clocks */ clk_disable(host->fclk); clk_disable(host->iclk); if (host->got_dbclk) clk_disable(host->dbclk); /* Turn the power off */ ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); /* Turn the power ON with given VDD 1.8 or 3.0v */ if (!ret) ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); clk_enable(host->iclk); clk_enable(host->fclk); if (host->got_dbclk) clk_enable(host->dbclk); if (ret != 0) goto err; OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); reg_val = OMAP_HSMMC_READ(host->base, HCTL); /* * If a MMC dual voltage card is detected, the set_ios fn calls * this fn with VDD bit set for 1.8V. Upon card removal from the * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. * * Cope with a bit of slop in the range ... per data sheets: * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, * but recommended values are 1.71V to 1.89V * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, * but recommended values are 2.7V to 3.3V * * Board setup code shouldn't permit anything very out-of-range. * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. */ if ((1 << vdd) <= MMC_VDD_23_24) reg_val |= SDVS18; else reg_val |= SDVS30; OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); set_sd_bus_power(host); return 0; err: dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); return ret; }
/* * MMC controller IRQ handler */ static irqreturn_t mmc_omap_irq(int irq, void *dev_id) { struct mmc_omap_host *host = dev_id; int end_cmd = 0, end_trans = 0, status; if (host->cmd == NULL && host->data == NULL) { OMAP_HSMMC_WRITE(host->base, STAT, OMAP_HSMMC_READ(host->base, STAT)); return IRQ_HANDLED; } status = OMAP_HSMMC_READ(host->base, STAT); dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); if (status & ERR) { if ((status & CMD_TIMEOUT) || (status & CMD_CRC)) { if (host->cmd) { if (status & CMD_TIMEOUT) host->cmd->error = -ETIMEDOUT; else host->cmd->error = -EILSEQ; end_cmd = 1; } if (host->data) mmc_dma_cleanup(host); } if ((status & DATA_TIMEOUT) || (status & DATA_CRC)) { if (host->data) { if (status & DATA_TIMEOUT) mmc_dma_cleanup(host); else host->data->error = -EILSEQ; end_trans = 1; } } if (status & CARD_ERR) { dev_dbg(mmc_dev(host->mmc), "Ignoring card err CMD%d\n", host->cmd->opcode); if (host->cmd) end_cmd = 1; if (host->data) end_trans = 1; } } OMAP_HSMMC_WRITE(host->base, STAT, status); if (end_cmd || (status & CC)) mmc_omap_cmd_done(host, host->cmd); if (end_trans || (status & TC)) mmc_omap_xfer_done(host, host->data); return IRQ_HANDLED; }
static void set_sd_bus_power(struct omap_hsmmc_host *host) { unsigned long i; OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDBP); for (i = 0; i < loops_per_jiffy; i++) { if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) break; cpu_relax(); } }
/* * Switch MMC operating voltage */ static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd) { u32 reg_val = 0; int ret; /* Disable the clocks */ clk_disable(host->fclk); clk_disable(host->iclk); clk_disable(host->dbclk); /* Turn the power off */ ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); if (ret != 0) goto err; /* Turn the power ON with given VDD 1.8 or 3.0v */ ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); if (ret != 0) goto err; clk_enable(host->fclk); clk_enable(host->iclk); clk_enable(host->dbclk); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); reg_val = OMAP_HSMMC_READ(host->base, HCTL); /* * If a MMC dual voltage card is detected, the set_ios fn calls * this fn with VDD bit set for 1.8V. Upon card removal from the * slot, mmc_omap_detect fn sets the VDD back to 3V. * * Only MMC1 supports 3.0V. MMC2 will not function if SDVS30 is * set in HCTL. */ if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) || ((1 << vdd) == MMC_VDD_33_34))) reg_val |= SDVS30; if ((1 << vdd) == MMC_VDD_165_195) reg_val |= SDVS18; OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDBP); return 0; err: dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); return ret; }
static void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) { unsigned int timeout, cycle_ns; uint32_t reg, clkd, dto = 0; reg = OMAP_HSMMC_READ(host->base, SYSCTL); clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; if (clkd == 0) clkd = 1; cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); timeout = req->data->timeout_ns / cycle_ns; timeout += req->data->timeout_clks; if (timeout) { while ((timeout & 0x80000000) == 0) { dto += 1; timeout <<= 1; } dto = 31 - dto; timeout <<= 1; if (timeout && dto) dto += 1; if (dto >= 13) dto -= 13; else dto = 0; if (dto > 14) dto = 14; } reg &= ~DTO_MASK; reg |= dto << DTO_SHIFT; OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); }
static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state) { int ret = 0; struct mmc_omap_host *host = platform_get_drvdata(pdev); if (host && host->suspended) return 0; if (host) { ret = mmc_suspend_host(host->mmc, state); if (ret == 0) { host->suspended = 1; mmc_clk_try_enable(host); OMAP_HSMMC_WRITE(host->base, ISE, 0); OMAP_HSMMC_WRITE(host->base, IE, 0); if (host->pdata->suspend) { ret = host->pdata->suspend(&pdev->dev, host->slot_id); if (ret) dev_dbg(mmc_dev(host->mmc), "Unable to handle MMC board" " level suspend\n"); } if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) { OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDVS30); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDBP); } mmc_clk_try_disable(host); if (cpu_is_omap2430()) clk_disable(host->dbclk); } } return ret; }
/* * MMC controller internal state machines reset * * Used to reset command or data internal state machines, using respectively * SRC or SRD bit of SYSCTL register * Can be called from interrupt context */ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, unsigned long bit) { unsigned long i = 0; unsigned long limit = (loops_per_jiffy * msecs_to_jiffies(MMC_TIMEOUT_MS)); OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | bit); while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && (i++ < limit)) cpu_relax(); if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) dev_err(mmc_dev(host->mmc), "Timeout waiting on controller reset in %s\n", __func__); }
static void set_data_timeout(struct omap_hsmmc_host *host, unsigned int timeout_ns, unsigned int timeout_clks) { uint32_t reg, dto = 14; reg = OMAP_HSMMC_READ(host->base, SYSCTL); reg &= ~DTO_MASK; reg |= dto << DTO_SHIFT; OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); }
/* * Send init stream sequence to card * before sending IDLE command */ static void send_init_stream(struct mmc_omap_host *host) { int reg = 0; unsigned long timeout; spin_lock(&host->inits_lock); disable_irq(host->irq); OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((reg != CC) && time_before(jiffies, timeout)) reg = OMAP_HSMMC_READ(host->base, STAT) & CC; OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); enable_irq(host->irq); spin_unlock(&host->inits_lock); }
static void omap2_hsmmc_restore_ctx(struct mmc_omap_host *host) { /* MMC : context restore */ OMAP_HSMMC_WRITE(host->base, HCTL, hsmmc_ctx[host->id].hctl); OMAP_HSMMC_WRITE(host->base, CAPA, hsmmc_ctx[host->id].capa); OMAP_HSMMC_WRITE(host->base, CON, hsmmc_ctx[host->id].con); OMAP_HSMMC_WRITE(host->base, ISE, hsmmc_ctx[host->id].ise); OMAP_HSMMC_WRITE(host->base, IE, hsmmc_ctx[host->id].ie); OMAP_HSMMC_WRITE(host->base, SYSCTL, hsmmc_ctx[host->id].sysctl); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDBP); }
static int omap_mmc_remove(struct platform_device *pdev) { struct mmc_omap_host *host = platform_get_drvdata(pdev); struct resource *res; u16 vdd = 0; /* * TODO: * The timer could kick in and turn off the clocks. * if mmc_remove_host touches the mmc module regs, this can * crash. So need to verify if mmc_remove_host indeed touches * the module regs. */ mmc_clk_try_enable(host); if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) { /* * Set the vdd back to 3V, * applicable for dual volt support. */ vdd = fls(host->mmc->ocr_avail) - 1; if (omap_mmc_switch_opcond(host, vdd) != 0) host->mmc->ios.vdd = vdd; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res) release_mem_region(res->start, res->end - res->start + 1); platform_set_drvdata(pdev, NULL); if (host) { mmc_remove_host(host->mmc); if (host->pdata->cleanup) host->pdata->cleanup(&pdev->dev); free_irq(host->irq, host); if (mmc_slot(host).card_detect_irq) free_irq(mmc_slot(host).card_detect_irq, host); flush_scheduled_work(); mmc_clk_try_disable(host); clk_put(host->fclk); clk_put(host->iclk); if (host->dbclk_enabled) { clk_disable(host->dbclk); clk_put(host->dbclk); } mmc_free_host(host->mmc); iounmap(host->base); } return 0; }
/* * Notify the core about command completion */ static void mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) { host->cmd = NULL; if (cmd->flags & MMC_RSP_PRESENT) { if (cmd->flags & MMC_RSP_136) { /* response type 2 */ cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); } else { /* response types 1, 1b, 3, 4, 5, 6 */ cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); } } if (host->data == NULL || cmd->error) { host->mrq = NULL; mmc_request_done(host->mmc, cmd->mrq); } }
// hooked function static void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) { uint32_t reg; // printk(KERN_INFO "MMC-fix: set_data_timeout called\n"); reg = OMAP_HSMMC_READ(host->base, SYSCTL); reg &= ~DTO_MASK; reg |= DTO << DTO_SHIFT; OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); if (0) HOOK_INVOKE(set_data_timeout, host, req); }
static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state) { int ret = 0; struct omap_hsmmc_host *host = platform_get_drvdata(pdev); if (host && host->suspended) return 0; if (host) { host->suspended = 1; if (host->pdata->suspend) { ret = host->pdata->suspend(&pdev->dev, host->slot_id); if (ret) { dev_dbg(mmc_dev(host->mmc), "Unable to handle MMC board" " level suspend\n"); host->suspended = 0; return ret; } } cancel_work_sync(&host->mmc_carddetect_work); mmc_host_enable(host->mmc); ret = mmc_suspend_host(host->mmc, state); if (ret == 0) { OMAP_HSMMC_WRITE(host->base, ISE, 0); OMAP_HSMMC_WRITE(host->base, IE, 0); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); mmc_host_disable(host->mmc); clk_disable(host->iclk); if (host->got_dbclk) clk_disable(host->dbclk); } else { host->suspended = 0; if (host->pdata->resume) { ret = host->pdata->resume(&pdev->dev, host->slot_id); if (ret) dev_dbg(mmc_dev(host->mmc), "Unmask interrupt failed\n"); } mmc_host_disable(host->mmc); } } return ret; }
static void omap2_hsmmc_save_ctx(struct mmc_omap_host *host) { /* MMC : context save */ hsmmc_ctx[host->id].hctl = OMAP_HSMMC_READ(host->base, HCTL); hsmmc_ctx[host->id].capa = OMAP_HSMMC_READ(host->base, CAPA); hsmmc_ctx[host->id].ise = OMAP_HSMMC_READ(host->base, ISE); hsmmc_ctx[host->id].ie = OMAP_HSMMC_READ(host->base, IE); hsmmc_ctx[host->id].con = OMAP_HSMMC_READ(host->base, CON); hsmmc_ctx[host->id].sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); }
static int omap_hsmmc_regs_show(struct seq_file *s, void *data) { struct mmc_host *mmc = s->private; struct omap_hsmmc_host *host = mmc_priv(mmc); int context_loss = 0; if (host->pdata->get_context_loss_count) context_loss = host->pdata->get_context_loss_count(host->dev); seq_printf(s, "mmc%d:\n" " enabled:\t%d\n" " dpm_state:\t%d\n" " nesting_cnt:\t%d\n" " ctx_loss:\t%d:%d\n" "\nregs:\n", mmc->index, mmc->enabled ? 1 : 0, host->dpm_state, mmc->nesting_cnt, host->context_loss, context_loss); if (host->suspended || host->dpm_state == OFF) { seq_printf(s, "host suspended, can't read registers\n"); return 0; } if (clk_enable(host->fclk) != 0) { seq_printf(s, "can't read the regs\n"); return 0; } seq_printf(s, "SYSCONFIG:\t0x%08x\n", OMAP_HSMMC_READ(host->base, SYSCONFIG)); seq_printf(s, "CON:\t\t0x%08x\n", OMAP_HSMMC_READ(host->base, CON)); seq_printf(s, "HCTL:\t\t0x%08x\n", OMAP_HSMMC_READ(host->base, HCTL)); seq_printf(s, "SYSCTL:\t\t0x%08x\n", OMAP_HSMMC_READ(host->base, SYSCTL)); seq_printf(s, "IE:\t\t0x%08x\n", OMAP_HSMMC_READ(host->base, IE)); seq_printf(s, "ISE:\t\t0x%08x\n", OMAP_HSMMC_READ(host->base, ISE)); seq_printf(s, "CAPA:\t\t0x%08x\n", OMAP_HSMMC_READ(host->base, CAPA)); clk_disable(host->fclk); return 0; }
/* * Work Item to notify the core about card insertion/removal */ static void mmc_omap_detect(struct work_struct *work) { u16 vdd = 0; struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, mmc_carddetect_work); if (host->carddetect) { if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) { /* * Set the VDD back to 3V when the card is removed * before the set_ios fn turns off the power. */ vdd = fls(host->mmc->ocr_avail) - 1; if (omap_mmc_switch_opcond(host, vdd) != 0) host->mmc->ios.vdd = vdd; } mmc_detect_change(host->mmc, (HZ * 200) / 1000); } else mmc_detect_change(host->mmc, (HZ * 50) / 1000); }
static int __init omap_mmc_probe(struct platform_device *pdev) { struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; struct mmc_host *mmc; struct mmc_omap_host *host = NULL; struct resource *res; int ret = 0, irq; u32 hctl, capa; if (pdata == NULL) { dev_err(&pdev->dev, "Platform Data is missing\n"); return -ENXIO; } if (pdata->nr_slots == 0) { dev_err(&pdev->dev, "No Slots\n"); return -ENXIO; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); if (res == NULL || irq < 0) return -ENXIO; res = request_mem_region(res->start, res->end - res->start + 1, pdev->name); if (res == NULL) return -EBUSY; mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); if (!mmc) { ret = -ENOMEM; goto err; } host = mmc_priv(mmc); host->mmc = mmc; host->pdata = pdata; host->use_dma = 1; host->dma_ch = -1; host->irq = irq; host->id = pdev->id; host->slot_id = 0; host->mapbase = res->start; host->base = ioremap(host->mapbase, SZ_4K); mmc->ops = &mmc_omap_ops; mmc->f_min = 400000; mmc->f_max = 52000000; sema_init(&host->sem, 1); host->iclk = clk_get(&pdev->dev, "mmchs_ick"); if (IS_ERR(host->iclk)) { ret = PTR_ERR(host->iclk); host->iclk = NULL; goto err; } host->fclk = clk_get(&pdev->dev, "mmchs_fck"); if (IS_ERR(host->fclk)) { ret = PTR_ERR(host->fclk); host->fclk = NULL; clk_put(host->iclk); goto err; } if (clk_enable(host->fclk) != 0) goto err; if (clk_enable(host->iclk) != 0) { clk_disable(host->fclk); clk_put(host->fclk); goto err; } host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); /* * MMC can still work without debounce clock. */ if (IS_ERR(host->dbclk)) dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n"); else if (clk_enable(host->dbclk) != 0) dev_dbg(mmc_dev(host->mmc), "Enabling debounce" " clk failed\n"); else host->dbclk_enabled = 1; mmc->ocr_avail = mmc_slot(host).ocr_mask; mmc->caps |= MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; if (pdata->conf.wire4) mmc->caps |= MMC_CAP_4_BIT_DATA; /* Only MMC1 supports 3.0V */ if (host->id == OMAP_MMC1_DEVID) { hctl = SDVS30; capa = VS30 | VS18; } else { hctl = SDVS18; capa = VS18; } OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | hctl); OMAP_HSMMC_WRITE(host->base, CAPA, OMAP_HSMMC_READ(host->base, CAPA) | capa); /* Set the controller to AUTO IDLE mode */ OMAP_HSMMC_WRITE(host->base, SYSCONFIG, OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); /* Set SD bus power bit */ OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDBP); /* Request IRQ for MMC operations */ ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, pdev->name, host); if (ret) { dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); goto irq_err; } /* Request IRQ for card detect */ if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) { ret = request_irq(mmc_slot(host).card_detect_irq, omap_mmc_cd_handler, IRQF_DISABLED, "MMC CD", host); if (ret) { dev_dbg(mmc_dev(host->mmc), "Unable to grab MMC CD IRQ"); free_irq(host->irq, host); goto irq_err; } } INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect); if (pdata->init != NULL) { if (pdata->init(&pdev->dev) != 0) { free_irq(mmc_slot(host).card_detect_irq, host); free_irq(host->irq, host); goto irq_err; } } OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); platform_set_drvdata(pdev, host); mmc_add_host(mmc); return 0; err: dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); if (host) mmc_free_host(mmc); return ret; irq_err: dev_dbg(mmc_dev(host->mmc), "Unable to configure MMC IRQs\n"); clk_disable(host->fclk); clk_disable(host->iclk); clk_put(host->fclk); clk_put(host->iclk); if (host->dbclk_enabled) { clk_disable(host->dbclk); clk_put(host->dbclk); } if (host) mmc_free_host(mmc); return ret; }
/* Routine to configure clock values. Exposed API to core */ static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct mmc_omap_host *host = mmc_priv(mmc); u16 dsor = 0; unsigned long regval; unsigned long timeout; switch (ios->power_mode) { case MMC_POWER_OFF: mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); break; case MMC_POWER_UP: mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd); break; } switch (mmc->ios.bus_width) { case MMC_BUS_WIDTH_4: OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); break; case MMC_BUS_WIDTH_1: OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); break; } if (host->id == OMAP_MMC1_DEVID) { /* Only MMC1 can operate at 3V/1.8V */ if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && (ios->vdd == DUAL_VOLT_OCR_BIT)) { /* * The mmc_select_voltage fn of the core does * not seem to set the power_mode to * MMC_POWER_UP upon recalculating the voltage. * vdd 1.8v. */ if (omap_mmc_switch_opcond(host, ios->vdd) != 0) dev_dbg(mmc_dev(host->mmc), "Switch operation failed\n"); } } if (ios->clock) { dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; if (dsor < 1) dsor = 1; if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) dsor++; if (dsor > 250) dsor = 250; } omap_mmc_stop_clock(host); regval = OMAP_HSMMC_READ(host->base, SYSCTL); regval = regval & ~(CLKD_MASK); regval = regval | (dsor << 6) | (DTO << 16); OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); /* Wait till the ICS bit is set */ timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2 && time_before(jiffies, timeout)) msleep(1); OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); if (ios->power_mode == MMC_POWER_ON) send_init_stream(host); if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) | OD); }
static int omap_hsmmc_enable_clks(struct mmc_omap_host *host) { unsigned long flags, timeout; int ret = 0; spin_lock_irqsave(&host->clk_lock, flags); if (host->clks_enabled) goto done; ret = clk_enable(host->iclk); if (ret) goto clk_en_err1; ret = clk_enable(host->fclk); if (ret) goto clk_en_err2; host->clks_enabled = 1; if (cpu_is_omap2430()) { /* * MMC can still work without debounce clock. */ if (IS_ERR(host->dbclk)) dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n"); else if (clk_enable(host->dbclk) != 0) dev_dbg(mmc_dev(host->mmc), "Enabling debounce" " clk failed\n"); else host->dbclk_enabled = 1; } if (!(host->pdata->context_loss) || (host->pdata->context_loss(host->dev) != host->off_counter)) { /* Coming out of OFF: * The SRA bit of SYSCTL reg has a wrong reset * value. * The bit resets automatically in subsequent * reads. Idealy it should have been 0 as per * the reset value of the register. * Wait for the reset to complete */ timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE && time_before(jiffies, timeout)) ; omap2_hsmmc_restore_ctx(host); } done: spin_unlock_irqrestore(&host->clk_lock, flags); return ret; clk_en_err2: clk_disable(host->iclk); clk_en_err1: dev_dbg(mmc_dev(host->mmc), "Unable to enable MMC clocks \n"); spin_unlock_irqrestore(&host->clk_lock, flags); return ret; }
static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state) { int ret = 0; int err = 0; struct mmc_omap_host *host = platform_get_drvdata(pdev); if (host && host->suspended) return 0; if (host) { host->suspended = 1; if (host->card_sleep){ dev_dbg(mmc_dev(host->mmc),"has been in sleep status\n"); } else if (mmc_card_can_sleep(host->mmc)){ err = mmc_card_sleep(host->mmc); if (err){ dev_dbg(mmc_dev(host->mmc),"MMC sleep command CMD5 return error\n"); } else{ host->card_sleep = 1; } } if (host->pdata->suspend) { ret = host->pdata->suspend(&pdev->dev, host->slot_id); if (ret) { dev_dbg(mmc_dev(host->mmc), "Unable to handle MMC board" " level suspend\n"); host->suspended = 0; return ret; } } cancel_work_sync(&host->mmc_carddetect_work); ret = mmc_suspend_host(host->mmc, state); if (ret == 0) { omap_hsmmc_enable_clks(host); OMAP_HSMMC_WRITE(host->base, ISE, 0); OMAP_HSMMC_WRITE(host->base, IE, 0); if (host->id == OMAP_MMC1_DEVID && !(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) { OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDVS30); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDBP); } omap_hsmmc_disable_clks(host); } else { host->suspended = 0; if (host->pdata->resume) { ret = host->pdata->resume(&pdev->dev, host->slot_id); if (ret) dev_dbg(mmc_dev(host->mmc), "Unmask interrupt failed\n"); } } } return ret; }
/* * MMC controller IRQ handler */ static irqreturn_t mmc_omap_irq(int irq, void *dev_id) { struct mmc_omap_host *host = dev_id; struct mmc_data *data; int end_cmd = 0, end_trans = 0, status; omap_hsmmc_enable_clks(host); if (host->cmd == NULL && host->data == NULL) { OMAP_HSMMC_WRITE(host->base, STAT, OMAP_HSMMC_READ(host->base, STAT)); return IRQ_HANDLED; } data = host->data; status = OMAP_HSMMC_READ(host->base, STAT); dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); if (status & ERR) { #ifdef CONFIG_MMC_DEBUG mmc_omap_report_irq(host, status); #endif if ((status & CMD_TIMEOUT) || (status & CMD_CRC) || (status & CMD_CEB) || (status & CMD_CIE)) { if (host->cmd) { if (status & CMD_TIMEOUT) { mmc_omap_reset_controller_fsm(host, SRC); host->cmd->error = -ETIMEDOUT; } else { host->cmd->error = -EILSEQ; } end_cmd = 1; } if (host->data) { mmc_dma_cleanup(host, -ETIMEDOUT); mmc_omap_reset_controller_fsm(host, SRD); } } if ((status & DATA_TIMEOUT) || (status & DATA_CRC) || (status & DATA_DEB)) { if (host->data) { if (status & DATA_TIMEOUT) mmc_dma_cleanup(host, -ETIMEDOUT); else mmc_dma_cleanup(host, -EILSEQ); mmc_omap_reset_controller_fsm(host, SRD); end_trans = 1; } } if (status & CARD_ERR) { dev_dbg(mmc_dev(host->mmc), "Ignoring card err CMD%d\n", host->cmd->opcode); if (host->cmd) end_cmd = 1; if (host->data) end_trans = 1; } } OMAP_HSMMC_WRITE(host->base, STAT, status); if (end_cmd || (status & CC)) mmc_omap_cmd_done(host, host->cmd); if (end_trans || (status & TC)) mmc_omap_xfer_done(host, data); /* Perform one dummy read to ensure the previous write actually went through */ status = OMAP_HSMMC_READ(host->base, STAT); return IRQ_HANDLED; }
/* Routine to configure clock values. Exposed API to core */ static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct mmc_omap_host *host = mmc_priv(mmc); u16 dsor = 0; unsigned long regval; unsigned long timeout; u32 con; del_timer_sync(&host->inact_timer); omap_hsmmc_enable_clks(host); switch (ios->power_mode) { case MMC_POWER_OFF: mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); /* * Reset interface voltage to 3V if it's 1.8V now; * only relevant on MMC-1, the others always use 1.8V. * * REVISIT: If we are able to detect cards after unplugging * a 1.8V card, this code should not be needed. */ if (host->id != OMAP_MMC1_DEVID) break; if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) { int vdd = fls(host->mmc->ocr_avail) - 1; if (omap_mmc_switch_opcond(host, vdd) != 0) host->mmc->ios.vdd = vdd; } break; case MMC_POWER_UP: mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd); break; } switch (mmc->ios.bus_width) { case MMC_BUS_WIDTH_8: OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) | DW8); break; case MMC_BUS_WIDTH_4: OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) & ~DW8); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); break; case MMC_BUS_WIDTH_1: OMAP_HSMMC_WRITE(host->base, CON, OMAP_HSMMC_READ(host->base, CON) & ~DW8); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); break; } if (host->id == OMAP_MMC1_DEVID) { /* Only MMC1 can interface at 3V without some flavor * of external transceiver; but they all handle 1.8V. */ if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && (ios->vdd == DUAL_VOLT_OCR_BIT)) { /* * The mmc_select_voltage fn of the core does * not seem to set the power_mode to * MMC_POWER_UP upon recalculating the voltage. * vdd 1.8v. */ if (omap_mmc_switch_opcond(host, ios->vdd) != 0) dev_dbg(mmc_dev(host->mmc), "Switch operation failed\n"); } } if (ios->clock) { dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; if (dsor < 1) dsor = 1; if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) dsor++; if (dsor > 250) dsor = 250; } omap_mmc_stop_clock(host); regval = OMAP_HSMMC_READ(host->base, SYSCTL); regval = regval & ~(CLKD_MASK); regval = regval | (dsor << 6) | (DTO << 16); OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); /* Wait till the ICS bit is set */ timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2 && time_before(jiffies, timeout)) msleep(1); OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); if (ios->power_mode == MMC_POWER_ON) send_init_stream(host); con = OMAP_HSMMC_READ(host->base, CON); if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) OMAP_HSMMC_WRITE(host->base, CON, con | OD); else OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); omap_hsmmc_disable_clks(host); }
/* Routine to configure clock values. Exposed API to core */ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct omap_hsmmc_host *host = mmc_priv(mmc); u16 dsor = 0; unsigned long regval; unsigned long timeout; u32 con; int do_send_init_stream = 0; mmc_host_enable(host->mmc); if (ios->power_mode != host->power_mode) { switch (ios->power_mode) { case MMC_POWER_OFF: mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); host->vdd = 0; break; case MMC_POWER_UP: mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd); host->vdd = ios->vdd; break; case MMC_POWER_ON: do_send_init_stream = 1; break; } host->power_mode = ios->power_mode; } /* FIXME: set registers based only on changes to ios */ con = OMAP_HSMMC_READ(host->base, CON); switch (mmc->ios.bus_width) { case MMC_BUS_WIDTH_8: OMAP_HSMMC_WRITE(host->base, CON, con | DW8); break; case MMC_BUS_WIDTH_4: OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); break; case MMC_BUS_WIDTH_1: OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); break; } if (host->id == OMAP_MMC1_DEVID) { /* Only MMC1 can interface at 3V without some flavor * of external transceiver; but they all handle 1.8V. */ if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && (ios->vdd == DUAL_VOLT_OCR_BIT)) { /* * The mmc_select_voltage fn of the core does * not seem to set the power_mode to * MMC_POWER_UP upon recalculating the voltage. * vdd 1.8v. */ if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) dev_dbg(mmc_dev(host->mmc), "Switch operation failed\n"); } } if (ios->clock) { dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; if (dsor < 1) dsor = 1; if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) dsor++; if (dsor > 250) dsor = 250; } omap_hsmmc_stop_clock(host); regval = OMAP_HSMMC_READ(host->base, SYSCTL); regval = regval & ~(CLKD_MASK); regval = regval | (dsor << 6) | (DTO << 16); OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); /* Wait till the ICS bit is set */ timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS && time_before(jiffies, timeout)) msleep(1); OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); if (do_send_init_stream) send_init_stream(host); con = OMAP_HSMMC_READ(host->base, CON); if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) OMAP_HSMMC_WRITE(host->base, CON, con | OD); else OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); if (host->power_mode == MMC_POWER_OFF) mmc_host_disable(host->mmc); else mmc_host_lazy_disable(host->mmc); }
/* * Restore the MMC host context, if it was lost as result of a * power state change. */ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) { struct mmc_ios *ios = &host->mmc->ios; struct omap_mmc_platform_data *pdata = host->pdata; int context_loss = 0; u32 hctl, capa, con; u16 dsor = 0; unsigned long timeout; if (pdata->get_context_loss_count) { context_loss = pdata->get_context_loss_count(host->dev); if (context_loss < 0) return 1; } dev_dbg(mmc_dev(host->mmc), "context was %slost\n", context_loss == host->context_loss ? "not " : ""); if (host->context_loss == context_loss) return 1; /* Wait for hardware reset */ timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE && time_before(jiffies, timeout)) ; /* Do software reset */ OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE && time_before(jiffies, timeout)) ; OMAP_HSMMC_WRITE(host->base, SYSCONFIG, OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); if (host->id == OMAP_MMC1_DEVID) { if (host->power_mode != MMC_POWER_OFF && (1 << ios->vdd) <= MMC_VDD_23_24) hctl = SDVS18; else hctl = SDVS30; capa = VS30 | VS18; } else { hctl = SDVS18; capa = VS18; } OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | hctl); OMAP_HSMMC_WRITE(host->base, CAPA, OMAP_HSMMC_READ(host->base, CAPA) | capa); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | SDBP); timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP && time_before(jiffies, timeout)) ; OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); /* Do not initialize card-specific things if the power is off */ if (host->power_mode == MMC_POWER_OFF) goto out; con = OMAP_HSMMC_READ(host->base, CON); switch (ios->bus_width) { case MMC_BUS_WIDTH_8: OMAP_HSMMC_WRITE(host->base, CON, con | DW8); break; case MMC_BUS_WIDTH_4: OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); break; case MMC_BUS_WIDTH_1: OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); OMAP_HSMMC_WRITE(host->base, HCTL, OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); break; } if (ios->clock) { dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; if (dsor < 1) dsor = 1; if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) dsor++; if (dsor > 250) dsor = 250; } OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS && time_before(jiffies, timeout)) ; OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); con = OMAP_HSMMC_READ(host->base, CON); if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) OMAP_HSMMC_WRITE(host->base, CON, con | OD); else OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); out: host->context_loss = context_loss; dev_dbg(mmc_dev(host->mmc), "context is restored\n"); return 0; }
/* * MMC controller IRQ handler */ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) { struct omap_hsmmc_host *host = dev_id; struct mmc_data *data; int end_cmd = 0, end_trans = 0, status; spin_lock(&host->irq_lock); if (host->mrq == NULL) { OMAP_HSMMC_WRITE(host->base, STAT, OMAP_HSMMC_READ(host->base, STAT)); /* Flush posted write */ OMAP_HSMMC_READ(host->base, STAT); spin_unlock(&host->irq_lock); return IRQ_HANDLED; } data = host->data; status = OMAP_HSMMC_READ(host->base, STAT); dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); if (status & ERR) { #ifdef CONFIG_MMC_DEBUG omap_hsmmc_report_irq(host, status); #endif if ((status & CMD_TIMEOUT) || (status & CMD_CRC)) { if (host->cmd) { if (status & CMD_TIMEOUT) { omap_hsmmc_reset_controller_fsm(host, SRC); host->cmd->error = -ETIMEDOUT; } else { host->cmd->error = -EILSEQ; } end_cmd = 1; } if (host->data || host->response_busy) { if (host->data) omap_hsmmc_dma_cleanup(host, -ETIMEDOUT); host->response_busy = 0; omap_hsmmc_reset_controller_fsm(host, SRD); } } if ((status & DATA_TIMEOUT) || (status & DATA_CRC)) { if (host->data || host->response_busy) { int err = (status & DATA_TIMEOUT) ? -ETIMEDOUT : -EILSEQ; if (host->data) omap_hsmmc_dma_cleanup(host, err); else host->mrq->cmd->error = err; host->response_busy = 0; omap_hsmmc_reset_controller_fsm(host, SRD); end_trans = 1; } } if (status & CARD_ERR) { dev_dbg(mmc_dev(host->mmc), "Ignoring card err CMD%d\n", host->cmd->opcode); if (host->cmd) end_cmd = 1; if (host->data) end_trans = 1; } } OMAP_HSMMC_WRITE(host->base, STAT, status); /* Flush posted write */ OMAP_HSMMC_READ(host->base, STAT); if (end_cmd || ((status & CC) && host->cmd)) omap_hsmmc_cmd_done(host, host->cmd); if ((end_trans || (status & TC)) && host->mrq) omap_hsmmc_xfer_done(host, data); spin_unlock(&host->irq_lock); return IRQ_HANDLED; }