/*
*********************************************************************************************************
* LCD_PLL_Calc
*
* Description : Calculate PLL frequence and divider depend on all kinds of lcd panel
*
* Arguments : sel <display channel>
* info <panel information>
* divider <divider pointer>
*
* Returns : success <frequence of pll >
* fail <-1>
*
* Note : 1.support hv/cpu/ttl panels which pixel frequence between 2MHz~297MHz
* 2.support all lvds panels, when pll can't reach (pixel clk x7),
* set pll to 381MHz(pllx1), which will depress the frame rate.
*********************************************************************************************************
*/
static __s32 LCD_PLL_Calc(__u32 sel, __panel_para_t * info, __u32 *divider)
{
__u32 lcd_dclk_freq; //Hz
__s32 pll_freq = -1;
lcd_dclk_freq = info->lcd_dclk_freq * 1000000;
if (info->lcd_if == 0 || info->lcd_if == 1 ||info->lcd_if == 2)// hv panel , CPU panel and ttl panel
{
if (lcd_dclk_freq > 2000000 && lcd_dclk_freq <= 297000000) //MHz
{
*divider = 297000000/(lcd_dclk_freq); //divider for dclk in tcon0
pll_freq = lcd_dclk_freq * (*divider);
}
else
{
return -1;
}
}
else if(info->lcd_if == 3) // lvds panel
{
__u32 clk_max;
if(OSAL_sw_get_ic_ver() > 0xA)
{
clk_max = 150000000;
}
else
{
clk_max = 108000000;//pixel clock can't be larger than 108MHz, limited by Video pll frequency
}
if(lcd_dclk_freq > clk_max)
{
lcd_dclk_freq = clk_max;
}
if (lcd_dclk_freq > 4000000) //pixel clk
{
pll_freq = lcd_dclk_freq * 7;
*divider = 7;
}
else
{
return -1;
}
}
return pll_freq;
}
__s32 LCD_PWM_EN(__u32 sel, __bool b_en)
{
if(gdisp.screen[sel].lcd_cfg.lcd_pwm_used)
{
user_gpio_set_t gpio_info[1];
__hdle hdl;
memcpy(gpio_info, &(gdisp.screen[sel].lcd_cfg.lcd_pwm), sizeof(user_gpio_set_t));
if((OSAL_sw_get_ic_ver() != 0xA) && (gpanel_info[sel].lcd_pwm_not_used == 0))
{
if(b_en)
{
pwm_enable(gpanel_info[sel].lcd_pwm_ch, b_en);
}
else
{
gpio_info->mul_sel = 0;
hdl = OSAL_GPIO_Request(gpio_info, 1);
OSAL_GPIO_Release(hdl, 2);
}
}
else
{
if(b_en != gpanel_info[sel].lcd_pwm_pol)
{
gpio_info->mul_sel = 1;
gpio_info->data = 1;
hdl = OSAL_GPIO_Request(gpio_info, 1);
OSAL_GPIO_Release(hdl, 2);
}
else
{
gpio_info->mul_sel = 1;
gpio_info->data = 0;
hdl = OSAL_GPIO_Request(gpio_info, 1);
OSAL_GPIO_Release(hdl, 2);
}
}
}
return 0;
}
//setting: 0, 1, 2,.... 255, 256
//pol==0: 0, 1, 2,.... 255, 256
//pol==1: 256, 255, 254, ... 1, 0
__s32 BSP_disp_lcd_set_bright(__u32 sel, __u32 bright)
{
__u32 duty_ns;
if((OSAL_sw_get_ic_ver() != 0xA) && (gpanel_info[sel].lcd_pwm_not_used == 0))
{
if(gpanel_info[sel].lcd_pwm_pol == 0)
{
duty_ns = (bright * gdisp.pwm[gpanel_info[sel].lcd_pwm_ch].period_ns + 128) / 256;
}
else
{
duty_ns = ((256- bright) * gdisp.pwm[gpanel_info[sel].lcd_pwm_ch].period_ns + 128) / 256;
}
pwm_set_duty_ns(gpanel_info[sel].lcd_pwm_ch, duty_ns);
}
gdisp.screen[sel].lcd_bright = bright;
return DIS_SUCCESS;
}
__s32 Disp_lcdc_init(__u32 sel)
{
LCD_get_sys_config(sel, &(gdisp.screen[sel].lcd_cfg));
lcdc_clk_init(sel);
lvds_clk_init();
lcdc_clk_on(sel); //??need to be open
LCDC_init(sel);
lcdc_clk_off(sel);
if(sel == 0)
{
OSAL_RegISR(INTC_IRQNO_LCDC0,0,Disp_lcdc_event_proc,(void*)sel,0,0);
#ifndef __LINUX_OSAL__
OSAL_InterruptEnable(INTC_IRQNO_LCDC0);
LCD_get_panel_funs_0(&lcd_panel_fun[sel]);
#endif
}
else
{
OSAL_RegISR(INTC_IRQNO_LCDC1,0,Disp_lcdc_event_proc,(void*)sel,0,0);
#ifndef __LINUX_OSAL__
OSAL_InterruptEnable(INTC_IRQNO_LCDC1);
LCD_get_panel_funs_1(&lcd_panel_fun[sel]);
#endif
}
if(gdisp.screen[sel].lcd_cfg.lcd_used)
{
if(lcd_panel_fun[sel].cfg_panel_info)
{
lcd_panel_fun[sel].cfg_panel_info(&gpanel_info[sel]);
}
else
{
LCD_get_panel_para(sel, &gpanel_info[sel]);
}
gpanel_info[sel].tcon_index = 0;
if((OSAL_sw_get_ic_ver() != 0xA) && (gpanel_info[sel].lcd_pwm_not_used == 0))
{
__pwm_info_t pwm_info;
pwm_info.enable = 0;
pwm_info.active_state = 1;
pwm_info.period_ns = 1000000 / gpanel_info[sel].lcd_pwm_freq;
if(gpanel_info[sel].lcd_pwm_pol == 0)
{
pwm_info.duty_ns = (192 * pwm_info.period_ns) / 256;
}
else
{
pwm_info.duty_ns = ((256 - 192) * pwm_info.period_ns) / 256;
}
pwm_set_para(gpanel_info[sel].lcd_pwm_ch, &pwm_info);
}
LCD_GPIO_init(sel);
}
return DIS_SUCCESS;
}
