/*
* Initialize the ANI register values with default (ini) values.
* This routine is called during a (full) hardware reset after
* all the registers are initialised from the INI.
*/
void
ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
int index;
u_int32_t val;
HALASSERT(chan != AH_NULL);
index = ar9300_get_ani_channel_index(ah, chan);
ani_state = &ahp->ah_ani[index];
ahp->ah_curani = ani_state;
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ver %d.%d opmode %u chan %d Mhz/0x%x macmode %d\n",
__func__, AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev,
AH_PRIVATE(ah)->ah_opmode, chan->ic_freq, chan->ic_flags, macmode);
val = OS_REG_READ(ah, AR_PHY_SFCORR);
ani_state->ini_def.m1_thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
ani_state->ini_def.m2_thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
ani_state->ini_def.m2_count_thr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
val = OS_REG_READ(ah, AR_PHY_SFCORR_LOW);
ani_state->ini_def.m1_thresh_low =
MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
ani_state->ini_def.m2_thresh_low =
MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
ani_state->ini_def.m2_count_thr_low =
MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
val = OS_REG_READ(ah, AR_PHY_SFCORR_EXT);
ani_state->ini_def.m1_thresh_ext = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
ani_state->ini_def.m2_thresh_ext = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
ani_state->ini_def.m1_thresh_low_ext =
MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
ani_state->ini_def.m2_thresh_low_ext =
MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
ani_state->ini_def.firstep =
OS_REG_READ_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP);
ani_state->ini_def.firstep_low =
OS_REG_READ_FIELD(
ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
ani_state->ini_def.cycpwr_thr1 =
OS_REG_READ_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1);
ani_state->ini_def.cycpwr_thr1_ext =
OS_REG_READ_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1);
/* these levels just got reset to defaults by the INI */
ani_state->spur_immunity_level = HAL_ANI_DEF_SPUR_IMMUNE_LVL;
ani_state->firstep_level = HAL_ANI_DEF_FIRSTEP_LVL;
ani_state->ofdm_weak_sig_detect_off = !HAL_ANI_USE_OFDM_WEAK_SIG;
ani_state->mrc_cck_off = !HAL_ANI_ENABLE_MRC_CCK;
ani_state->cycle_count = 0;
}
void
ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)
{
u_int32_t val;
HAL_CHANNEL_INTERNAL *chan = NULL;
const struct ieee80211_channel *c;
int i, ichain, rx_chain_status;
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_BOOL asleep = ahp->ah_chip_full_sleep;
c = AH_PRIVATE(ah)->ah_curchan;
if (c != NULL)
chan = ath_hal_checkchannel(ah, c);
// XXX TODO: just always wake up all chips?
if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
}
val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
ss->ss_fft_period = MS(val, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD);
ss->ss_period = MS(val, AR_PHY_SPECTRAL_SCAN_PERIOD);
ss->ss_count = MS(val, AR_PHY_SPECTRAL_SCAN_COUNT);
ss->ss_short_report = (val & AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT) ? 1:0;
ss->ss_spectral_pri = ( val & AR_PHY_SPECTRAL_SCAN_PRIORITY_HI) ? 1:0;
OS_MEMZERO(ss->ss_nf_cal, sizeof(ss->ss_nf_cal));
OS_MEMZERO(ss->ss_nf_pwr, sizeof(ss->ss_nf_cal));
ss->ss_nf_temp_data = 0;
if (chan != NULL) {
rx_chain_status = OS_REG_READ(ah, AR_PHY_RX_CHAINMASK) & 0x7;
for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
ichain = i % 3;
if (rx_chain_status & (1 << ichain)) {
ss->ss_nf_cal[i] =
ar9300_noise_floor_get(ah, chan->channel, ichain);
ss->ss_nf_pwr[i] =
ar9300_noise_floor_power_get(ah, chan->channel, ichain);
}
}
ss->ss_nf_temp_data = OS_REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4, AR_PHY_BB_THERM_ADC_4_LATEST_THERM);
} else {
HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
"%s: chan is NULL - no ss nf values\n", __func__);
}
if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
}
}
