//----------------------------------------------------------------------------
void StopAssistTimer()
{
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
OUTREG16(A_TCU_TCNT(TCU_IDLE_TIMER_CHN), 0x0000);
free_irq(EIRQ_TCU2_BASE + TCU_IDLE_TIMER_CHN);
}
void __init chip_clocksource_init(unsigned int base)
{
struct clocksource *cs = &clocksource_timer;
clksrc_base = base;
#if USE_GLOBAL_TIMER
PERI_W(GT_CONTROL,0x1); //Enable
//calculate the value of mult //cycle= ( time(ns) *mult ) >> shift
cs->mult = clocksource_khz2mult(GLB_TIMER_FREQ_KHZ, cs->shift);//PERICLK = CPUCLK/2
#else
/* setup timer 1 as free-running clocksource */
//make sure timer 1 is disable
CLRREG16(clksrc_base, TIMER_ENABLE);
//set max period
OUTREG16(clksrc_base+(0x2<<2),0xffff);
OUTREG16(clksrc_base+(0x3<<2),0xffff);
//enable timer 1
SETREG16(clksrc_base, TIMER_ENABLE);
// TODO: need to double check
//calculate the value of mult //cycle= ( time(ns) *mult ) >> shift
cs->mult = clocksource_khz2mult(GLB_TIMER_FREQ_KHZ, cs->shift); //Mstar timer =>12Mhz,
#endif
clocksource_register(cs);
}
DPI_STATUS DPI_Init_PLL(unsigned int mipi_pll_clk_ref,unsigned int mipi_pll_clk_div1,unsigned int mipi_pll_clk_div2)
{
#if 1
MIPITX_CFG0_REG con0 = DSI_PHY_REG_DPI->MIPITX_CON0;
MIPITX_CFG1_REG con1 = DSI_PHY_REG_DPI->MIPITX_CON1;
#ifdef DPI_MIPI_API
enable_mipi(MT65XX_MIPI_TX, "DPI");
#endif
#ifdef BUILD_UBOOT
OUTREG16(0xc2080858, 0x8000);
OUTREG16(0xc20a3824, 0x4008);
MASKREG16(0xc20a380c, 0x000c, 0x0000); //default value is 0x7008, but should be 0x7000
#else
OUTREG16(0xf2080858, 0x8000); //??
OUTREG16(0xf20a3824, 0x4008);
MASKREG16(0xf20a380c, 0x000c, 0x0000); //default value is 0x7008, but should be 0x7000
#endif
MASKREG16(PLL_SOURCE, 0x0010, 0x0010); //
con1.RG_PLL_DIV1 = mipi_pll_clk_div1;
con1.RG_PLL_DIV2 = mipi_pll_clk_div2;
con0.PLL_CLKR_EN = 1;
con0.PLL_EN = 1;
con0.RG_DPI_EN = 1;
// Set to DSI_PHY_REG
OUTREG32(&DSI_PHY_REG_DPI->MIPITX_CON0, AS_UINT32(&con0));
OUTREG32(&DSI_PHY_REG_DPI->MIPITX_CON1, AS_UINT32(&con1));
#endif
return DPI_STATUS_OK;
}
static BOOL McBSPRead(OMAP2420_McBSP_REGS *pMcBSP, PWORD pwData)
{
WORD wReg, wAttempts;
*pwData = INREG16(&pMcBSP->usMCBSP_DRR1);
wReg = INREG16(&pMcBSP->usMCBSP_SPCR1);
if (wReg & MCBSP_RSYNCERR)
{
OUTREG16(&pMcBSP->usMCBSP_SPCR1, wReg & (~MCBSP_RSYNCERR));
DEBUGMSG(ZONE_AC, (L"AC: McBSPRead FAILED on RSYNC\r\n"));
}
else
{
for (wAttempts = 0; wAttempts < 1000; wAttempts++)
{
wReg = INREG16(&pMcBSP->usMCBSP_SPCR1);
if (wReg & MCBSP_RRDY)
{
return TRUE;
}
}
OUTREG16(&pMcBSP->usMCBSP_SPCR1, wReg & (~MCBSP_RRST));
Sleep(1);
OUTREG16(&pMcBSP->usMCBSP_SPCR1, wReg | MCBSP_RRST);
Sleep(1);
DEBUGMSG(ZONE_AC, (L"AC: McBSPRead FAILED on RRDY\r\n"));
}
return FALSE;
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//Note:
// frequence=[(OSC_CLOCK / 4) / 0xffff+1,((OSC_CLOCK / 4) / 100)]
// IF OSC_CLOCK=12,000,000 THEN frequence=[190,120000]
// mode: bit0---InitLevel 0--LowLevel 1--HightLevel
// bit1---ShutDown 0--Gracefull 1--Abrutp
void pwm_init(unsigned int chn, unsigned int frequence, unsigned int mode)
{
unsigned int full_counter;
if ((frequence < ((OSC_CLOCK) / 0xffff) + 1) || (frequence > (OSC_CLOCK/100)))
{
printf("The frequence of pwm shoud be in [%d,%d]\n",
(((OSC_CLOCK) / 0xffff)+1), ((OSC_CLOCK/100)) );
return;
}
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
OUTREG32(A_GPIO_PXFUNS(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXSELC(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXPES(4), 1 << (20 + chn));
OUTREG16(A_TCU_TCSR(chn), TCU_CLK_EXTAL);
full_counter = (OSC_CLOCK) / frequence;
OUTREG16(A_TCU_TDFR(chn), full_counter);
OUTREG16(A_TCU_TDHR(chn), 0x0000);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
SETREG32((A_TCU_TCSR(chn)), (mode & 0x3) << 8);
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
}
static BOOL McBSPWrite(OMAP2420_McBSP_REGS *pMcBSP, WORD wData)
{
WORD wReg, wAttempts;
OUTREG16(&pMcBSP->usMCBSP_DXR1, wData);
wReg = INREG16(&pMcBSP->usMCBSP_SPCR2);
if (wReg & MCBSP_XSYNCERR)
{
OUTREG16(&pMcBSP->usMCBSP_SPCR2, wReg & (~MCBSP_XSYNCERR));
DEBUGMSG(ZONE_AC, (L"AC: McBSPWrite FAILED on XSYNC\r\n"));
}
else
{
for (wAttempts = 0; wAttempts < 1000; wAttempts++)
{
wReg = INREG16(&pMcBSP->usMCBSP_SPCR2);
if (wReg & MCBSP_XRDY)
{
return TRUE;
}
}
OUTREG16(&pMcBSP->usMCBSP_SPCR2, wReg & (~MCBSP_XRST));
Sleep(1);
OUTREG16(&pMcBSP->usMCBSP_SPCR2, wReg | MCBSP_XRST);
Sleep(1);
DEBUGMSG(ZONE_AC, (L"AC: McBSPWrite FAILED on XRDY\r\n"));
}
return FALSE;
}
void hw_reset(void)
{
printf("hw_reset\n");
OUTREG16(A_WDT_TCSR, WDT_CLK_EXTAL);
SETREG16(A_WDT_TCSR, WDT_CLK_PRESCALE_CLK1024);
OUTREG16(A_WDT_TDR, 3);
OUTREG16(A_WDT_TCNT, 0);
SETREG8(A_WDT_TCER, WDT_ENABLE);
while (1);
}
void JZ_StartIdleTimer(int time, void (*handler)(unsigned int))
{
unsigned int match_counter;
if ( time>(65535/(OSC_CLOCK / 256000)) )
{
printf("The msec for idletimer shoud be in [0,%d]\n",65535/(OSC_CLOCK /256000));
return ;
}
JZ_InitIdleTimer(handler);
match_counter = ((OSC_CLOCK /1000) * time) / 256;
OUTREG16(A_TCU_TDFR(TCU_IDLE_TIMER_CHN), match_counter);
OUTREG16(A_TCU_TESR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
}
void JZ_InitIdleTimer(void (*handler)(unsigned int))
{
while(IdleTimer_Flag);
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
OUTREG16(A_TCU_TCSR(TCU_IDLE_TIMER_CHN), TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK256);
OUTREG16(A_TCU_TDFR(TCU_IDLE_TIMER_CHN), 0xffff);
OUTREG16(A_TCU_TDHR(TCU_IDLE_TIMER_CHN), 0xffff);
OUTREG16(A_TCU_TCNT(TCU_IDLE_TIMER_CHN), 0x0000);
OUTREG32(A_TCU_TFCR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
OUTREG32(A_TCU_TMCR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
request_irq(EIRQ_TCU2_BASE + TCU_IDLE_TIMER_CHN, handler, 0);
}
void pwm_set_duty(unsigned int chn, unsigned int percent)
{
unsigned int full_cycles;
static unsigned int old_percent=1;
if (percent == 108)
{
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
return;
}
if (percent > 100)
{
printf("The percent of PWM should be within 100\n");
return;
}
if (percent == 0)
{
CLRREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
if(old_percent!=0)
{
__gpio_as_output(4*32+20+chn);
__gpio_clear_pin(4*32+20+chn);
}
old_percent=0;
}
else
{
if(old_percent==0)
{
OUTREG32(A_GPIO_PXFUNS(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXSELC(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXPES(4), 1 << (20 + chn));
}
full_cycles = INREG16(A_TCU_TDFR(chn));
CLRREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG16(A_TCU_TDHR(chn), full_cycles - (full_cycles * percent) / 110);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
old_percent=percent;
}
}
//----------------------------------------------------------------------------
static void delayupdate(unsigned int *addr)
{ int rest,t,i,flag=0,counter2 = 0;
//JZ_StopTimerEx(TCU_IDLE_TIMER_CHN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
rest = INREG16(A_TCU_TCNT(TCU_IDLE_TIMER_CHN))/(OSC_CLOCK / 256000);
if(g_counter>0)
{
counter2 = g_counter-rest ;
g_counter = MIN(rest,*addr);
}
else
g_counter=*addr;
for(i=0;i<NUM;i++)
{
if(( counter[i]== 0 ) && ( flag== 1 ))
{
counter[i]=addr;
flag = 0 ;
}
else
{
t = *counter[i];
t-= counter2;
*counter[i] = MAX(0,t);
}
}
JZ_StartIdleTimer(g_counter, idle_timerhandle2);
}
void WriteReg16(uint32 addr, uint16 value)
{
if (gInfo.sharedInfo->chipType == S3_TRIO64)
WritePIO(addr, 2, value);
else
OUTREG16(addr, value);
}
////////////////////////////////////////////////////
// 功能: codec 寄存器读出
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static unsigned char codec_reg_read(unsigned char addr)
{
AIC_RW_CODEC_START();
OUTREG16(AIC_RGADW, (addr << RGADW_ADDR_BIT));
return (INREG8(AIC_RGDAT));
}
void Stop_PerformanceCounter(void)
{
printf("WARMING: Performance Counter will STOP!!!\n");
OUTREG32(A_TCU_TMSR, TCU_OSTMST);
OUTREG16(A_TCU_TECR, TCU_OSTCL);
}
void JZ_StopTicker(void)
{
printf("WARMING: System Timer will STOP!!!\n");
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(TCU_SYSTEM_TIMER_CHN));
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_SYSTEM_TIMER_CHN));
}
static void timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned short ctl=TIMER_INTERRUPT;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
interval = (PIU_TIMER_FREQ_KHZ*1000 / HZ) ;
OUTREG16(clkevt_base + ADDR_TIMER_MAX_LOW, (interval &0xffff));
OUTREG16(clkevt_base + ADDR_TIMER_MAX_HIGH, (interval >>16));
ctl|=TIMER_ENABLE;
SETREG16(clkevt_base, ctl);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
ctl|=TIMER_TRIG;
SETREG16(clkevt_base, ctl);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
break;
}
}
void __init edison_init_timer(void)
{
#if 1 //calculate mult and shift for sched_clock
u32 shift,mult;
#endif
#ifdef CONFIG_MSTAR_EDISON_BD_FPGA
GLB_TIMER_FREQ_KHZ= 24*1000 ; // PERIPHCLK = CPU Clock / 2,
// div 2 later,when CONFIG_GENERIC_CLOCKEVENTS
// clock event will handle this value
//clock event will handle this value
#else
GLB_TIMER_FREQ_KHZ=(query_frequency()*1000/2); // PERIPHCLK = CPU Clock / 2
// div 2 later,when CONFIG_GENERIC_CLOCKEVENTS
// clock event will handle this value
#endif
printk("Global Timer Frequency = %d MHz\n",GLB_TIMER_FREQ_KHZ/1000);
printk("CPU Clock Frequency = %d MHz\n",query_frequency());
#ifdef CONFIG_HAVE_SCHED_CLOCK
#if 1 //calculate mult and shift for sched_clock
clocks_calc_mult_shift(&mult, &shift, (u32)(GLB_TIMER_FREQ_KHZ*1000), NSEC_PER_SEC,0);
printk("fre = %d, mult= %u, shift= %u\n",(GLB_TIMER_FREQ_KHZ*1000),mult,shift);
SC_SHIFT=shift;
SC_MULT=mult;
#endif
mstar_sched_clock_init((void __iomem *)(PERI_VIRT+0x200), (unsigned long)(GLB_TIMER_FREQ_KHZ*1000));
#endif
#ifdef CONFIG_GENERIC_CLOCKEVENTS
//mstar_local_timer_init(((void __iomem *)PERI_ADDRESS(PERI_PHYS+0x600))); //private_timer base
edison_clocksource_init(EDISON_BASE_REG_TIMER1_PA);
edison_clockevents_init(INT_WDT_IRQ);
#else
setup_irq(E_FIQ_EXTIMER0 , &edison_timer_irq);
//enable timer interrupt
SETREG16(EDISON_BASE_REG_TIMER0_PA,TIMER_INTERRUPT);
//set interval
interval = ( 12*1000*1000 ) / HZ ;
OUTREG16(EDISON_BASE_REG_TIMER0_PA + ADDR_TIMER_MAX_LOW, (interval & 0xffff));
OUTREG16(EDISON_BASE_REG_TIMER0_PA + ADDR_TIMER_MAX_HIGH, (interval >>16));
//trig timer0
SETREG16(EDISON_BASE_REG_TIMER0_PA, TIMER_TRIG);
#endif
}
static void ARKSetupForScreenToScreenCopy(ScrnInfoPtr pScrn, int xdir,
int ydir, int rop, unsigned int planemask,
int trans_color)
{
ARKPtr pARK = ARKPTR(pScrn);
cmd_flags = 0;
if (trans_color != -1) {
if (pScrn->bitsPerPixel <= 16)
OUTREG16(TRANS_COLOR, trans_color);
else {
OUTREG16(TRANS_COLOR, trans_color & 0xffff);
OUTREG16(TRANS_COLOR_HI, trans_color >> 16);
}
cmd_flags = STENCIL_GENERATED;
OUTREG16(COLOR_MIX_SEL, rop | 0x0500);
} else {
//------------------------------------------------------------------------------
// Stop Timer 2
//------------------------------------------------------------------------------
void SHxStopTimer2 (void)
{
volatile SH4_TMU_REGS *pTMURegs = OALPAtoUA(SH4_REG_PA_TMU);
//
// Diable timer2 interrupt
//
OUTREG16(&pTMURegs->TCR2, INREG16(&pTMURegs->TCR2) & ~TMU_TCR_UNIE);
}
//------------------------------------------------------------------------------
// Start timer 2 (parameter - interrupt interval in micro-seconds)
//------------------------------------------------------------------------------
void SHxStartTimer2 (DWORD dwUSec)
{
DWORD dwCount;
volatile SH4_TMU_REGS *pTMURegs = OALPAtoUA(SH4_REG_PA_TMU);
if (!dwUSec) {
//
// Use default rate (1 MS)
//
dwUSec = 1000;
} else if (dwUSec < 20) {
//
// Rate specified: at least 20us
//
dwUSec = 20;
}
dwCount = (dwUSec * g_oalTimer.countsPerMSec) / 1000;
//
// Init timer2 and enable timer2 interrupt
//
// make sure timer2 is topped
OUTREG8(&pTMURegs->TSTR, INREG8(&pTMURegs->TSTR) & ~TMU_TSTR_STR2);
// initialize timer constant and count register
OUTREG32(&pTMURegs->TCOR2, dwCount);
OUTREG32(&pTMURegs->TCNT2, dwCount);
// enable timer2 interrupts
// Enable underflow interrupts
OUTREG16(&pTMURegs->TCR2, INREG16(&pTMURegs->TCR2) | TMU_TCR_UNIE);
// Clear any pending interrupts
OUTREG16(&pTMURegs->TCR2, INREG16(&pTMURegs->TCR2) & ~TMU_TCR_UNF);
// start timer2
OUTREG8(&pTMURegs->TSTR, INREG8(&pTMURegs->TSTR) | TMU_TSTR_STR2);
}
////////////////////////////////////////////////////
// 功能: codec 寄存器清除
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static void codec_reg_clear(unsigned char addr, unsigned char data)
{
unsigned int temp = addr << RGADW_ADDR_BIT;
AIC_RW_CODEC_START();
OUTREG16(AIC_RGADW, temp);
temp |= (INREG8(AIC_RGDAT) & (~data));
OUTREG32(AIC_RGADW, temp);
OUTREG32(AIC_RGADW, (temp | AIC_RGADW_RGWR));
AIC_RW_CODEC_STOP();
}
void JZ_StartTimerEx(int chn, int frequence, void (*handler)())
{
unsigned int match_counter;
if ( (frequence<((OSC_CLOCK / 4) / 0xffff)+1) || (frequence>(OSC_CLOCK / 400)) )
{
printf("The frequence of timer shoud be in [%d,%d]\n",
(((OSC_CLOCK / 4) / 0xffff)+1),((OSC_CLOCK / 400)));
return ;
}
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
OUTREG16(A_TCU_TCSR(chn), TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK4);
match_counter = (OSC_CLOCK / 4) / frequence;
OUTREG16(A_TCU_TDFR(chn), match_counter);
OUTREG16(A_TCU_TDHR(chn), match_counter);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG32(A_TCU_TFCR, TCU_INTR_FLAG(chn));
OUTREG32(A_TCU_TMCR, TCU_INTR_FLAG(chn));
request_irq(EIRQ_TCU2_BASE + chn, handler, 0);
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
enable_irq(EIRQ_TCU2_BASE + chn);
}
//----------------------------------------------------------------------------
int osIdleDelay(unsigned short ticks)
{
unsigned int savesr;
int count;
int cur_ticks = 0;
if(ticks == 0) ticks = 1;
if(ticks > 60) return 0;
savesr = spin_lock_irqsave();
//printf("set ticks = %d\n",ticks);
//printf("a:%x\n",INREG16(A_TCU_TER) & TCU_TIMER(TCU_IDLE_TIMER_CHN));
if(INREG16(A_TCU_TER) & TCU_TIMER(TCU_IDLE_TIMER_CHN))
{
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
int fullcount = INREG16(A_TCU_TDFR(TCU_IDLE_TIMER_CHN));
if(!(TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN) & INREG16(A_TCU_TFR)))
{
//printf("aa\n");
count = INREG16(A_TCU_TCNT(TCU_IDLE_TIMER_CHN));
if(count < fullcount - 10)
OUTREG16(A_TCU_TDFR(TCU_IDLE_TIMER_CHN), count + 10);
}//else printf("bb\n");
}else
{
cur_ticks = ticks;
if(cur_ticks >= 60) cur_ticks = 60;
//printf("a:cur_ticks %x\n",cur_ticks);
count = ((OSC_CLOCK / 1000 * MSEC_PER_TICK) * cur_ticks + 255) / 256;
//printf("a:%x\n",count);
OUTREG16(A_TCU_TDFR(TCU_IDLE_TIMER_CHN), count);
}
OUTREG16(A_TCU_TESR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
OUTREG32(A_TCU_TMCR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
spin_unlock_irqrestore(savesr);
return 0;
}
void JZ_StartTicker(unsigned int TicksPerSec)
{
unsigned int match_counter;
// 1. Start TCU Clock
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
// 2. Disable TCU.
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_SYSTEM_TIMER_CHN));
// 3. Config Clock
OUTREG16(A_TCU_TCSR(TCU_SYSTEM_TIMER_CHN), TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK64);
// 4. Config Counter According to Clock
match_counter = (OSC_CLOCK / 64) / TicksPerSec;
OUTREG16(A_TCU_TDFR(TCU_SYSTEM_TIMER_CHN), match_counter);
OUTREG16(A_TCU_TDHR(TCU_SYSTEM_TIMER_CHN), match_counter);
OUTREG16(A_TCU_TCNT(TCU_SYSTEM_TIMER_CHN), 0x0000);
// 5. Clear TCU Intr Flag and Enable Intr
OUTREG32(A_TCU_TFCR, TCU_INTR_FLAG(TCU_SYSTEM_TIMER_CHN));
OUTREG32(A_TCU_TMCR, TCU_INTR_FLAG(TCU_SYSTEM_TIMER_CHN));
// 6. Enable TCU_SYSTEM_TIMER_CHN TCU
OUTREG16(A_TCU_TESR, TCU_TIMER(TCU_SYSTEM_TIMER_CHN));
// 7. Enable IRQ
enable_irq(IRQ_SYSTEM_TIMER);
}
int Init_PerformanceCounter(void)
{
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_OSTCL);
OUTREG32(A_OST_CSR, TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK4);
OUTREG32(A_OST_DR, 0xFFFFFFFF);
OUTREG32(A_OST_CNT, 0);
SETREG32(A_TCU_TESR, TCU_OSTEN);
return ((OSC_CLOCK / 4 ) / 1000000);
}
static int serverworks_configure(void)
{
struct aper_size_info_lvl2 *current_size;
u32 temp;
u8 enable_reg;
u16 cap_reg;
current_size = A_SIZE_LVL2(agp_bridge->current_size);
/* Get the memory mapped registers */
pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);
if (!serverworks_private.registers) {
printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
return -ENOMEM;
}
OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a);
OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE,
agp_bridge->gatt_bus_addr);
cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND);
cap_reg &= ~0x0007;
cap_reg |= 0x4;
OUTREG16(serverworks_private.registers, SVWRKS_COMMAND, cap_reg);
pci_read_config_byte(serverworks_private.svrwrks_dev,
SVWRKS_AGP_ENABLE, &enable_reg);
enable_reg |= 0x1; /* Agp Enable bit */
pci_write_config_byte(serverworks_private.svrwrks_dev,
SVWRKS_AGP_ENABLE, enable_reg);
serverworks_tlbflush(NULL);
agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
/* Fill in the mode register */
pci_read_config_dword(serverworks_private.svrwrks_dev,
agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
enable_reg &= ~0x3;
pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
enable_reg |= (1<<6);
pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
return 0;
}
static void ARKSetupForSolidFill(ScrnInfoPtr pScrn, int color,
int rop, unsigned int planemask)
{
ARKPtr pARK = ARKPTR(pScrn);
OUTREG16(FG_COLOR, color);
/* ARK color mix matches X raster-ops */
OUTREG16(COLOR_MIX_SEL, (rop | (rop << 8)));
switch (pScrn->bitsPerPixel) {
case 8:
if ((planemask & 0xff) == 0xff)
cmd_flags = DISABLE_PLANEMASK;
else {
OUTREG16(WRITE_PLANEMASK, planemask);
cmd_flags = 0;
}
break;
case 16:
if ((planemask & 0xffff) == 0xffff)
cmd_flags = DISABLE_PLANEMASK;
else {
OUTREG16(WRITE_PLANEMASK, planemask);
cmd_flags = 0;
}
break;
case 32:
OUTREG16(FG_COLOR_HI, color >> 16);
if ((planemask & 0xffffff) == 0xffffff)
cmd_flags = DISABLE_PLANEMASK;
else {
OUTREG16(WRITE_PLANEMASK, planemask);
cmd_flags = 0;
}
break;
}
curx = cury = -1;
}
static int timer_set_next_event(unsigned long next, struct clock_event_device *evt)
{
//stop timer
//OUTREG16(clkevt_base, 0x0);
//set period
OUTREG16(clkevt_base + ADDR_TIMER_MAX_LOW, (next &0xffff));
OUTREG16(clkevt_base + ADDR_TIMER_MAX_HIGH, (next >>16));
//enable timer
SETREG16(clkevt_base, TIMER_TRIG|TIMER_INTERRUPT);//default
return 0;
}
/*
* IRQ handler for the timer
*/
static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
//printk("t");
/* clear the interrupt */
evt_timer_cnt=INREG16(clkevt_base+(0x3<<2));
OUTREG16(clkevt_base+(0x3<<2),evt_timer_cnt);
//enable timer
//SETREG16(clkevt_base, TIMER_TRIG);//default
evt->event_handler(evt);
return IRQ_HANDLED;
}
static irqreturn_t chip_timer_interrupt(int irq, void *dev_id)
{
unsigned short tmp;
timer_tick();
//stop timer
CLRREG16(chip_BASE_REG_TIMER0_PA, TIMER_TRIG);
//set interval
//interval = (CLOCK_TICK_RATE / HZ);
OUTREG16(chip_BASE_REG_TIMER0_PA + ADDR_TIMER_MAX_LOW, (interval &0xffff));
OUTREG16(chip_BASE_REG_TIMER0_PA + ADDR_TIMER_MAX_HIGH, (interval >>16));
//trig timer0
SETREG16(chip_BASE_REG_TIMER0_PA, TIMER_TRIG);
return IRQ_HANDLED;
}