TI_HD47780_T* ti_hd47780_init(unsigned int*  cntl_reg, unsigned int*  data_reg, 
		                      unsigned char  disp_row, unsigned char  disp_col,
		                      unsigned int   cpufreq_in)
{
    TI_HD47780_T *p_hd;
    char func_set = 0x20;

    if(PAL_osMemAlloc(0, sizeof(TI_HD47780_T), 0, &p_hd) != PAL_SOK) {
        return NULL;    
    }
      
    PAL_osMemSet(p_hd, 0, sizeof(TI_HD47780_T));

    p_hd->cntl_reg = cntl_reg;
    p_hd->data_reg = data_reg;
    p_hd->disp_row = disp_row;
    p_hd->disp_col = disp_col;
    hd47780_cpufreq        = cpufreq_in;

    if(!(p_hd->disp_row % 2))
        func_set |= 0x08;
    
    
    TI_LIDD_DELAY_US(200, p_hd->cntl_reg);
    
    if(*(p_hd->cntl_reg) & LCD_HD47780_BUSY)
    {
            PAL_osMemFree(0, p_hd, sizeof(TI_HD47780_T));
            return 0;
    }
    
    *p_hd->cntl_reg = func_set | 0x10;
    
    TI_LIDD_DELAY_US(50, p_hd->cntl_reg);

    return (p_hd);
}
Esempio n. 2
0
/*! \fn static void init_cppi_tx(mpeg_process_private* priv)
 **************************************************************************
 *  \brief Init Mpeg Encap TX
 *  \return  0 or error code
 */
static void init_cppi_tx(mpeg_process_private* priv)
{
    int i_bd=0;
	Uint32 outstream_idx;

    priv->irq_counter = -1;
    priv->frames_processed = -1;
    for(outstream_idx=0; outstream_idx<MAX_MPEG_CHNS; ++outstream_idx)
        priv->encap_out_streams[outstream_idx].acc_frames = 0;

    printk("TX Init CPPI: open free descriptor queue\n");
    /* open free descriptor queue */
    {
        Cppi4Queue queue = {PAL_CPPI41_QUEUE_MGR_PARTITION_SR, PAL_CPPI41_SR_MPEG_ENCAP_FD_EMB_Q_NUM};
        if(!(priv->txMpegEncap_free_queue_hnd = PAL_cppi4QueueOpen(priv->pal_hnd, queue)))
        {
            printk(KERN_ERR "%s: Unable to open free desc queue %d priority channel\n", __FUNCTION__, PAL_CPPI41_SR_MPEG_ENCAP_FD_EMB_Q_NUM);
            goto err;
        }
    }

    printk("TX Init CPPI: allocate descriptors\n");
    /*
     * Define free embedded descriptors for channel
     * --------------------------------------------
     */
    printk("%s: Allocate descriptors to the embedded free queues\n", __FUNCTION__);
    if(!(priv->txMpegEncap_pdpool = PAL_cppi4AllocDesc (priv->pal_hnd, PAL_CPPI41_QUEUE_MGR_PARTITION_SR, DMAC_MPEG_ENCAP_RX_EMBEDDED_BD_NUM, MPEG_ENCAP_BD_SIZE)))
    {
        printk(KERN_ERR "%s: Unable to init BD pool\n", __FUNCTION__);
        goto err;        
    }

    printk("TX Init CPPI: Fill free discriptor queue\n");
    for (i_bd = 0; i_bd < DMAC_MPEG_ENCAP_RX_EMBEDDED_BD_NUM; i_bd++) 
    {
        Cppi4ExtEmbdDesc *bd = (Cppi4ExtEmbdDesc *)GET_MPEG_ENCAP_BD_PTR(priv->txMpegEncap_pdpool, i_bd);

        PAL_osMemSet(bd, 0, MPEG_ENCAP_BD_SIZE);
        bd->descInfo     = CPPI41_EM_DESCINFO_DTYPE_EMBEDDED | CPPI41_EM_DESCINFO_SLOTCNT_MPEG_ENCAP;
        bd->tagInfo      = 0;
        bd->pktInfo      = (PAL_CPPI4_HOSTDESC_PKT_TYPE_ETH << CPPI41_EM_PKTINFO_PKTTYPE_SHIFT) 
                            | (CPPI41_EM_PKTINFO_RETPOLICY_RETURN) 
                            | (0 << CPPI41_EM_PKTINFO_PROTSPEC_SHIFT) 
                            | (PAL_CPPI41_QUEUE_MGR_PARTITION_SR << CPPI41_EM_PKTINFO_RETQMGR_SHIFT) 
                            | (PAL_CPPI41_SR_MPEG_ENCAP_FD_EMB_Q_NUM << CPPI41_EM_PKTINFO_RETQ_SHIFT);
        PAL_CPPI4_CACHE_WRITEBACK(bd, CPPI4_BD_LENGTH_FOR_CACHE);
        PAL_cppi4QueuePush (priv->txMpegEncap_free_queue_hnd, (Ptr) PAL_CPPI4_VIRT_2_PHYS(bd), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(MPEG_ENCAP_BD_SIZE), 0);        
    }

    printk("TX Init CPPI: Create CPGMAC TX handler\n");
    {
        Cppi4Queue queue = {PAL_CPPI41_QUEUE_MGR_PARTITION_SR, 212};
        if(!(priv->txCpgmac_queue_hnd = PAL_cppi4QueueOpen(priv->pal_hnd, queue)))
        {
            printk(KERN_ERR "%s: Unable to open cpgmac  queue\n", __FUNCTION__);
            goto err;
        }
    }

    priv->try2alloc = 0;
    priv->outof_buf = 0;
    priv->outof_pd = 0;

    printk("TX Init CPPI: open mpeg TX channel\n");
    /*
     * Open MPEG-OUT TX channel and is TX-queue 
     * --------------------------------------------
     */
    {
        /* DMA channel configuration */
        {
            PAL_Cppi4TxChHnd mpegOutTxChHdl;
            volatile Cppi4TxChInitCfg mpegOutTxChInfo;
    
            mpegOutTxChInfo.chNum = MPEGOUT_CPPI4x_CHNUM;
            mpegOutTxChInfo.dmaNum = PAL_CPPI41_DMA_BLOCK1; 
            mpegOutTxChInfo.tdQueue.qMgr = PAL_CPPI41_QUEUE_MGR_PARTITION_SR;
            mpegOutTxChInfo.tdQueue.qNum = 218;
            mpegOutTxChInfo.defDescType = CPPI41_DESC_TYPE_EMBEDDED;
    
            mpegOutTxChHdl = PAL_cppi4TxChOpen (priv->pal_hnd, (Cppi4TxChInitCfg *)(&mpegOutTxChInfo), NULL);
            if(mpegOutTxChHdl == NULL)
            {
                printk("%s: Unable to open %d channel \n", __FUNCTION__, mpegOutTxChInfo.chNum);
                goto err;
            }
            PAL_cppi4EnableTxChannel (mpegOutTxChHdl, NULL);
            priv->txMpegOut_chn_hdl = &mpegOutTxChHdl;
        }
        /* TX queue channel configuration */
        {
            Cppi4Queue queue;   /* used generically */     

            queue.qNum = 218;
            queue.qMgr = PAL_CPPI41_QUEUE_MGR_PARTITION_SR;
            if(!(priv->txMpegOut_queue_hnd = PAL_cppi4QueueOpen(priv->pal_hnd, queue)))
            {
                printk("%s: unable to open Tx Queue #%d!\n", __FUNCTION__, queue.qNum);                
                goto err;
            }
        }
    }


    printk("TX Init CPPI pass\n");
    return;
err:
    printk("TX Init CPPI failed\n");
    return;
}
Esempio n. 3
0
/*! \fn static void init_cppi_rx(mpeg_process_private* priv)
 **************************************************************************
 *  \brief Init Mpeg Encap RX
 *  \return  0 or error code
 */
static void init_cppi_rx(mpeg_process_private* priv)
{
    int i_bd=0;

    priv->irq_counter = -1;
    priv->frames_processed = -1;
    priv->host_forwarded = -1;
    priv->try2alloc = -1;
    priv->outof_buf = -1;
    priv->outof_pd = -1;

    printk("RX Init CPPI: open free descriptor queue\n");
    /* open free descriptor queue */
    {
        Cppi4Queue queue = {PAL_CPPI41_QUEUE_MGR_PARTITION_SR, PAL_CPPI41_SR_MPEG_FD_EMB_Q_NUM};
        if(!(priv->rxMpeg_free_queue_hnd = PAL_cppi4QueueOpen(priv->pal_hnd, queue)))
        {
            printk(KERN_ERR "%s: Unable to open free desc queue %d priority channel\n", __FUNCTION__, PAL_CPPI41_SR_MPEG_FD_EMB_Q_NUM);
            goto err;
        }
    }

    printk("RX Init CPPI: allocate descriptors\n");
    /*
     * Define free embedded descriptors for channel
     * --------------------------------------------
     */
    printk("%s: Allocate descriptors to the embedded free queues\n", __FUNCTION__);

    if(!(priv->rxMpeg_pdpool = PAL_cppi4AllocDesc (priv->pal_hnd, PAL_CPPI41_QUEUE_MGR_PARTITION_SR, DMAC_MPEG_RX_EMBEDDED_BD_NUM, 64)))
    {
        printk(KERN_ERR "%s: Unable to init BD pool\n", __FUNCTION__);
        goto err;        
    }

    printk("RX Init CPPI: Fill free discriptor queue\n");
    for (i_bd = 0; i_bd < DMAC_MPEG_RX_EMBEDDED_BD_NUM; i_bd++) 
    {
        Cppi4EmbdDesc *bd = (Cppi4EmbdDesc *)GET_MPEG_BD_PTR(priv->rxMpeg_pdpool, i_bd);

        PAL_osMemSet(bd, 0, 64);
        bd->descInfo     = CPPI41_EM_DESCINFO_DTYPE_EMBEDDED | CPPI41_EM_DESCINFO_SLOTCNT_MPEG;
        bd->tagInfo      = 0;
        bd->pktInfo      = (PAL_CPPI4_HOSTDESC_PKT_TYPE_GENERIC << CPPI41_EM_PKTINFO_PKTTYPE_SHIFT) 
                            | (CPPI41_EM_PKTINFO_RETPOLICY_RETURN) 
                            | (1 << CPPI41_EM_PKTINFO_PROTSPEC_SHIFT) 
                            | (PAL_CPPI41_QUEUE_MGR_PARTITION_SR << CPPI41_EM_PKTINFO_RETQMGR_SHIFT) 
                            | (PAL_CPPI41_SR_MPEG_FD_EMB_Q_NUM << CPPI41_EM_PKTINFO_RETQ_SHIFT);
        PAL_CPPI4_CACHE_WRITEBACK(bd, CPPI4_BD_LENGTH_FOR_CACHE);
        PAL_cppi4QueuePush (priv->rxMpeg_free_queue_hnd, (Ptr) PAL_CPPI4_VIRT_2_PHYS(bd), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(64), 0);        
    }


    printk("RX Init CPPI: Set DMA channel\n");
    {
        volatile Cppi4RxChInitCfg MpegRxChInfo;
        PAL_Cppi4RxChHnd MpegRxChHdl;

        MpegRxChInfo.chNum = MPEG_CPPI4x_RX_DMA_CHNUM;
        MpegRxChInfo.dmaNum = 1;
        MpegRxChInfo.rxCompQueue.qMgr = PAL_CPPI41_QUEUE_MGR_PARTITION_SR;
        MpegRxChInfo.rxCompQueue.qNum = PAL_CPPI41_SR_MPEG_HOST_RX_Q_NUM;
        MpegRxChInfo.sopOffset = 0; // SOF 
        MpegRxChInfo.retryOnStarvation = 0;

        MpegRxChInfo.defDescType = CPPI41_DESC_TYPE_EMBEDDED;
        MpegRxChInfo.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI41_QUEUE_MGR_PARTITION_SR;
        MpegRxChInfo.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI41_SR_MPEG_FD_EMB_Q_NUM;
        MpegRxChInfo.u.embeddedPktCfg.numBufSlot = CPPI41_EM_DESCINFO_SLOTCNT_MPEG;
        MpegRxChInfo.u.embeddedPktCfg.sopSlotNum = 0;
        MpegRxChInfo.u.embeddedPktCfg.fBufPool[0].bMgr = 0;  
        MpegRxChInfo.u.embeddedPktCfg.fBufPool[0].bPool = 2; 

        printk("%s: Call PAL_cppi4RxChOpen channel=%d, REF_CNT=%u BUF COUNT=%u\n", __FUNCTION__, MpegRxChInfo.chNum, BMGR0_POOL06_REF_CNT,
			   BMGR0_POOL06_BUF_COUNT);
        MpegRxChHdl = PAL_cppi4RxChOpen (priv->pal_hnd, (Cppi4RxChInitCfg *)(&MpegRxChInfo), NULL);
        if(MpegRxChHdl == NULL)
        {
            printk(KERN_ERR "%s: Unable to open %d channel \n", __FUNCTION__, MpegRxChInfo.chNum);
            goto err;
        }
        PAL_cppi4EnableRxChannel (MpegRxChHdl, NULL);
        priv->rxMpeg_chan_hnd = MpegRxChHdl;
    }

    printk("RX Init CPPI: Init accumulator\n");
    {
        unsigned int i = 0;
        //for (i=0; i<MPEG_CPPI4x_RX_Q_COUNT; ++i)
        {
            Cppi4Queue rx_queue = {PAL_CPPI41_QUEUE_MGR_PARTITION_SR, PAL_CPPI41_SR_MPEG_HOST_RX_Q_NUM};
            
            if(!(priv->rx_queue_hnd[i] = PAL_cppi4QueueOpen(priv->pal_hnd, rx_queue)))
            {
                printk(KERN_ERR "%s: Unable to open rx queue %d channel\n", __FUNCTION__, PAL_CPPI41_SR_MPEG_HOST_RX_Q_NUM);
                goto err;
            }

            priv->rxAcc_chan_hnd[i] = NULL;
            if(mpeg_init_acc_chan(priv->pal_hnd, PAL_CPPI41_MPEG_ACC_RX_CH_NUM, rx_queue, &priv->rxAcc_chan_hnd[i]))
            {
                printk(KERN_ERR "%s: Unable to open accumulator channel for %d priority channel\n", __FUNCTION__, i);
                goto err;                        
            }
            priv->rxAcc_chan_list_base[i] = priv->rxAcc_chan_list[i] = PAL_cppi4AccChGetNextList(priv->rxAcc_chan_hnd[i]);
        }
    }

    /* request the Rx IRQs */            
    if(request_irq (MPEG_RXINT_NUM, mpegEncapRootIsr, IRQF_DISABLED, "mpeg", priv))
    {
        printk(KERN_ERR "%s: unable to get IRQ #%d!\n", __FUNCTION__, MPEG_RXINT_NUM);
        goto err;
    }
    priv->irq_counter = 0;
    priv->frames_processed = 0;
    priv->host_forwarded = 0;

    printk("RX Init RX CPPI pass\n");
    return;
err:
    printk("RX Init RX CPPI failed\n");
    return;
}