void athn_pci_attach(struct device *parent, struct device *self, void *aux) { struct athn_pci_softc *psc = (struct athn_pci_softc *)self; struct athn_softc *sc = &psc->sc_sc; struct pci_attach_args *pa = aux; const char *intrstr; pci_intr_handle_t ih; pcireg_t memtype, reg; pci_product_id_t subsysid; int error; sc->sc_dmat = pa->pa_dmat; psc->sc_pc = pa->pa_pc; psc->sc_tag = pa->pa_tag; sc->ops.read = athn_pci_read; sc->ops.write = athn_pci_write; sc->ops.write_barrier = athn_pci_write_barrier; /* * Get the offset of the PCI Express Capability Structure in PCI * Configuration Space (Linux hardcodes it as 0x60.) */ error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, &psc->sc_cap_off, NULL); if (error != 0) { /* Found. */ sc->sc_disable_aspm = athn_pci_disable_aspm; sc->flags |= ATHN_FLAG_PCIE; } /* * Clear device-specific "PCI retry timeout" register (41h) to prevent * PCI Tx retries from interfering with C3 CPU state. */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40); if (reg & 0xff00) pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00); /* * Set the cache line size to a reasonable value if it is 0. * Change latency timer; default value yields poor results. */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); if (PCI_CACHELINE(reg) == 0) { reg &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); reg |= 8 << PCI_CACHELINE_SHIFT; } reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); reg |= 168 << PCI_LATTIMER_SHIFT; pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg); /* Determine if bluetooth is also supported (combo chip.) */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); subsysid = PCI_PRODUCT(reg); if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA || subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA) sc->flags |= ATHN_FLAG_BTCOEX3WIRE; else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE) sc->flags |= ATHN_FLAG_BTCOEX2WIRE; /* Map control/status registers. */ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &psc->sc_st, &psc->sc_sh, NULL, &psc->sc_mapsize, 0); if (error != 0) { printf(": can't map mem space\n"); return; } if (pci_intr_map(pa, &ih) != 0) { printf(": can't map interrupt\n"); return; } intrstr = pci_intr_string(psc->sc_pc, ih); psc->sc_ih = pci_intr_establish(psc->sc_pc, ih, IPL_NET, athn_intr, sc, sc->sc_dev.dv_xname); if (psc->sc_ih == NULL) { printf(": can't establish interrupt"); if (intrstr != NULL) printf(" at %s", intrstr); printf("\n"); return; } printf(": %s\n", intrstr); athn_attach(sc); }
int pci_probe_device(struct pci_softc *sc, pcitag_t tag, int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) { pci_chipset_tag_t pc = sc->sc_pc; struct pci_attach_args pa; pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; #ifdef __HAVE_PCI_MSI_MSIX pcireg_t cap; int off; #endif int ret, pin, bus, device, function, i, width; int locs[PCICF_NLOCS]; pci_decompose_tag(pc, tag, &bus, &device, &function); /* a driver already attached? */ if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) return 0; bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); if (PCI_HDRTYPE_TYPE(bhlcr) > 2) return 0; id = pci_conf_read(pc, tag, PCI_ID_REG); /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); /* Invalid vendor ID value? */ if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) return 0; /* XXX Not invalid, but we've done this ~forever. */ if (PCI_VENDOR(id) == 0) return 0; /* Collect memory range info */ memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); i = 0; switch (PCI_HDRTYPE_TYPE(bhlcr)) { case PCI_HDRTYPE_PPB: endbar = PCI_MAPREG_PPB_END; break; case PCI_HDRTYPE_PCB: endbar = PCI_MAPREG_PCB_END; break; default: endbar = PCI_MAPREG_END; break; } for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { struct pci_range *r; pcireg_t type; width = 4; if (pci_mapreg_probe(pc, tag, bar, &type) == 0) continue; if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) width = 8; r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; if (pci_mapreg_info(pc, tag, bar, type, &r->r_offset, &r->r_size, &r->r_flags) != 0) break; if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) && (r->r_size == 0x1000000)) { struct pci_range *nr; /* * this has to be a mach64 * split things up so each half-aperture can * be mapped PREFETCHABLE except the last page * which may contain registers */ r->r_size = 0x7ff000; r->r_flags = BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE; nr = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; nr->r_offset = r->r_offset + 0x800000; nr->r_size = 0x7ff000; nr->r_flags = BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE; } } } pa.pa_iot = sc->sc_iot; pa.pa_memt = sc->sc_memt; pa.pa_dmat = sc->sc_dmat; pa.pa_dmat64 = sc->sc_dmat64; pa.pa_pc = pc; pa.pa_bus = bus; pa.pa_device = device; pa.pa_function = function; pa.pa_tag = tag; pa.pa_id = id; pa.pa_class = pciclass; /* * Set up memory, I/O enable, and PCI command flags * as appropriate. */ pa.pa_flags = sc->sc_flags; /* * If the cache line size is not configured, then * clear the MRL/MRM/MWI command-ok flags. */ if (PCI_CACHELINE(bhlcr) == 0) { pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); } if (sc->sc_bridgetag == NULL) { pa.pa_intrswiz = 0; pa.pa_intrtag = tag; } else { pa.pa_intrswiz = sc->sc_intrswiz + device; pa.pa_intrtag = sc->sc_intrtag; } intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); pin = PCI_INTERRUPT_PIN(intr); pa.pa_rawintrpin = pin; if (pin == PCI_INTERRUPT_PIN_NONE) { /* no interrupt */ pa.pa_intrpin = 0; } else { /* * swizzle it based on the number of busses we're * behind and our device number. */ pa.pa_intrpin = /* XXX */ ((pin + pa.pa_intrswiz - 1) % 4) + 1; } pa.pa_intrline = PCI_INTERRUPT_LINE(intr); #ifdef __HAVE_PCI_MSI_MSIX if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { /* * XXX Should we enable MSI mapping ourselves on * systems that have it disabled? */ if (cap & PCI_HT_MSI_ENABLED) { uint64_t addr; if ((cap & PCI_HT_MSI_FIXED) == 0) { addr = pci_conf_read(pc, tag, off + PCI_HT_MSI_ADDR_LO); addr |= (uint64_t)pci_conf_read(pc, tag, off + PCI_HT_MSI_ADDR_HI) << 32; } else addr = PCI_HT_MSI_FIXED_ADDR; /* * XXX This will fail to enable MSI on systems * that don't use the canonical address. */ if (addr == PCI_HT_MSI_FIXED_ADDR) { pa.pa_flags |= PCI_FLAGS_MSI_OKAY; pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; } } } #endif if (match != NULL) { ret = (*match)(&pa); if (ret != 0 && pap != NULL) *pap = pa; } else { struct pci_child *c; locs[PCICF_DEV] = device; locs[PCICF_FUNCTION] = function; c = &sc->PCI_SC_DEVICESC(device, function); pci_conf_capture(pc, tag, &c->c_conf); if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) c->c_psok = true; else c->c_psok = false; c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, pciprint, config_stdsubmatch); ret = (c->c_dev != NULL); } return ret; }
void fxp_pci_attach(struct device *parent, struct device *self, void *aux) { struct fxp_softc *sc = (struct fxp_softc *)self; struct pci_attach_args *pa = aux; pci_chipset_tag_t pc = pa->pa_pc; pci_intr_handle_t ih; const char *chipname = NULL; const char *intrstr = NULL; bus_size_t iosize; if (pci_mapreg_map(pa, FXP_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0, &sc->sc_st, &sc->sc_sh, NULL, &iosize, 0)) { printf(": can't map i/o space\n"); return; } sc->sc_dmat = pa->pa_dmat; sc->sc_revision = PCI_REVISION(pa->pa_class); /* * Allocate our interrupt. */ if (pci_intr_map(pa, &ih)) { printf(": couldn't map interrupt\n"); bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); return; } intrstr = pci_intr_string(pc, ih); sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc, self->dv_xname); if (sc->sc_ih == NULL) { printf(": couldn't establish interrupt"); if (intrstr != NULL) printf(" at %s", intrstr); printf("\n"); bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); return; } switch (PCI_PRODUCT(pa->pa_id)) { case PCI_PRODUCT_INTEL_8255x: case PCI_PRODUCT_INTEL_82559: case PCI_PRODUCT_INTEL_82559ER: { chipname = "i82557"; if (sc->sc_revision >= FXP_REV_82558_A4) chipname = "i82558"; if (sc->sc_revision >= FXP_REV_82559_A0) chipname = "i82559"; if (sc->sc_revision >= FXP_REV_82559S_A) chipname = "i82559S"; if (sc->sc_revision >= FXP_REV_82550) chipname = "i82550"; if (sc->sc_revision >= FXP_REV_82551_E) chipname = "i82551"; break; } break; default: chipname = "i82562"; break; } if (chipname != NULL) printf(", %s", chipname); /* * Cards for which we should WRITE TO THE EEPROM * to turn off dynamic standby mode to avoid * a problem where the card will fail to resume when * entering the IDLE state. We use this nasty if statement * and corresponding pci dev numbers directly so that people * know not to add new cards to this unless you are really * certain what you are doing and are not going to end up * killing people's eeproms. */ if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) && (PCI_PRODUCT(pa->pa_id) == 0x2449 || (PCI_PRODUCT(pa->pa_id) > 0x1030 && PCI_PRODUCT(pa->pa_id) < 0x1039) || (PCI_PRODUCT(pa->pa_id) == 0x1229 && (sc->sc_revision >= 8 && sc->sc_revision <= 16)))) sc->sc_flags |= FXPF_DISABLE_STANDBY; /* * enable PCI Memory Write and Invalidate command */ if (sc->sc_revision >= FXP_REV_82558_A4) if (PCI_CACHELINE(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG))) { pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, PCI_COMMAND_INVALIDATE_ENABLE | pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)); sc->sc_flags |= FXPF_MWI_ENABLE; } /* Do generic parts of attach. */ if (fxp_attach(sc, intrstr)) { /* Failed! */ pci_intr_disestablish(pc, sc->sc_ih); bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); return; } }
static void artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) { struct pciide_channel *pc; int chan; u_int32_t dma_ctl; u_int32_t cacheline_len; aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, "bus-master DMA support present"); sc->sc_dma_ok = 1; /* * Errata #4 says that if the cacheline length is not set correctly, * we can get corrupt MWI and Memory-Block-Write transactions. */ cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, PCI_BHLC_REG)); if (cacheline_len == 0) { aprint_verbose(", but unused (cacheline size not set in PCI conf)\n"); sc->sc_dma_ok = 0; return; } /* * Final step of the work-around is to force the DMA engine to use * the cache-line length information. */ dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); sc->sc_wdcdev.dma_arg = sc; sc->sc_wdcdev.dma_init = pciide_dma_init; sc->sc_wdcdev.dma_start = pciide_dma_start; sc->sc_wdcdev.dma_finish = pciide_dma_finish; sc->sc_dma_iot = sc->sc_ba5_st; sc->sc_dmat = pa->pa_dmat; if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & PCIIDE_OPTIONS_NODMA) { aprint_verbose( ", but unused (forced off by config file)\n"); sc->sc_dma_ok = 0; return; } /* * Set up the default handles for the DMA registers. * Just reserve 32 bits for each handle, unless space * doesn't permit it. */ for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { pc = &sc->pciide_channels[chan]; if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, &pc->dma_iohs[IDEDMA_CMD]) != 0 || bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, &pc->dma_iohs[IDEDMA_CTL]) != 0 || bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, &pc->dma_iohs[IDEDMA_TBL]) != 0) { sc->sc_dma_ok = 0; aprint_verbose(", but can't subregion registers\n"); return; } } aprint_verbose("\n"); }
static void tlp_pci_attach(device_t parent, device_t self, void *aux) { struct tulip_pci_softc *psc = device_private(self); struct tulip_softc *sc = &psc->sc_tulip; struct pci_attach_args *pa = aux; pci_chipset_tag_t pc = pa->pa_pc; pci_intr_handle_t ih; const char *intrstr = NULL; bus_space_tag_t iot, memt; bus_space_handle_t ioh, memh; int ioh_valid, memh_valid, i, j; const struct tulip_pci_product *tpp; prop_data_t ea; uint8_t enaddr[ETHER_ADDR_LEN]; uint32_t val = 0; pcireg_t reg; int error; bus_size_t iosize = 0, memsize = 0; sc->sc_dev = self; sc->sc_devno = pa->pa_device; psc->sc_pc = pa->pa_pc; psc->sc_pcitag = pa->pa_tag; LIST_INIT(&psc->sc_intrslaves); tpp = tlp_pci_lookup(pa); if (tpp == NULL) { printf("\n"); panic("tlp_pci_attach: impossible"); } sc->sc_chip = tpp->tpp_chip; /* * By default, Tulip registers are 8 bytes long (4 bytes * followed by a 4 byte pad). */ sc->sc_regshift = 3; /* * No power management hooks. * XXX Maybe we should add some! */ sc->sc_flags |= TULIPF_ENABLED; /* * Get revision info, and set some chip-specific variables. */ sc->sc_rev = PCI_REVISION(pa->pa_class); switch (sc->sc_chip) { case TULIP_CHIP_21140: if (sc->sc_rev >= 0x20) sc->sc_chip = TULIP_CHIP_21140A; break; case TULIP_CHIP_21142: if (sc->sc_rev >= 0x20) sc->sc_chip = TULIP_CHIP_21143; break; case TULIP_CHIP_82C168: if (sc->sc_rev >= 0x20) sc->sc_chip = TULIP_CHIP_82C169; break; case TULIP_CHIP_MX98713: if (sc->sc_rev >= 0x10) sc->sc_chip = TULIP_CHIP_MX98713A; break; case TULIP_CHIP_MX98715: if (sc->sc_rev >= 0x20) sc->sc_chip = TULIP_CHIP_MX98715A; if (sc->sc_rev >= 0x25) sc->sc_chip = TULIP_CHIP_MX98715AEC_X; if (sc->sc_rev >= 0x30) sc->sc_chip = TULIP_CHIP_MX98725; break; case TULIP_CHIP_WB89C840F: sc->sc_regshift = 2; break; case TULIP_CHIP_AN985: /* * The AN983 and AN985 are very similar, and are * differentiated by a "signature" register that * is like, but not identical, to a PCI ID register. */ reg = pci_conf_read(pc, pa->pa_tag, 0x80); switch (reg) { case 0x09811317: sc->sc_chip = TULIP_CHIP_AN985; break; case 0x09851317: sc->sc_chip = TULIP_CHIP_AN983; break; default: /* Unknown -- use default. */ break; } break; case TULIP_CHIP_AX88140: if (sc->sc_rev >= 0x10) sc->sc_chip = TULIP_CHIP_AX88141; break; case TULIP_CHIP_DM9102: if (sc->sc_rev >= 0x30) sc->sc_chip = TULIP_CHIP_DM9102A; break; default: /* Nothing. */ break; } aprint_normal(": %s Ethernet, pass %d.%d\n", tlp_chip_name(sc->sc_chip), (sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf); switch (sc->sc_chip) { case TULIP_CHIP_21040: if (sc->sc_rev < 0x20) { aprint_normal_dev(self, "21040 must be at least pass 2.0\n"); return; } break; case TULIP_CHIP_21140: if (sc->sc_rev < 0x11) { aprint_normal_dev(self, "21140 must be at least pass 1.1\n"); return; } break; default: /* Nothing. */ break; } /* * Check to see if the device is in power-save mode, and * being it out if necessary. */ switch (sc->sc_chip) { case TULIP_CHIP_21140: case TULIP_CHIP_21140A: case TULIP_CHIP_21142: case TULIP_CHIP_21143: case TULIP_CHIP_MX98713A: case TULIP_CHIP_MX98715: case TULIP_CHIP_MX98715A: case TULIP_CHIP_MX98715AEC_X: case TULIP_CHIP_MX98725: case TULIP_CHIP_DM9102: case TULIP_CHIP_DM9102A: case TULIP_CHIP_AX88140: case TULIP_CHIP_AX88141: case TULIP_CHIP_RS7112: /* * Clear the "sleep mode" bit in the CFDA register. */ reg = pci_conf_read(pc, pa->pa_tag, TULIP_PCI_CFDA); if (reg & (CFDA_SLEEP|CFDA_SNOOZE)) pci_conf_write(pc, pa->pa_tag, TULIP_PCI_CFDA, reg & ~(CFDA_SLEEP|CFDA_SNOOZE)); break; default: /* Nothing. */ break; } /* power up chip */ if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && error != EOPNOTSUPP) { aprint_error_dev(self, "cannot activate %d\n", error); return; } /* * Map the device. */ ioh_valid = (pci_mapreg_map(pa, TULIP_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &iosize) == 0); memh_valid = (pci_mapreg_map(pa, TULIP_PCI_MMBA, PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, NULL, &memsize) == 0); if (memh_valid) { sc->sc_st = memt; sc->sc_sh = memh; psc->sc_mapsize = memsize; if (ioh_valid) { bus_space_unmap(iot, ioh, iosize); ioh_valid = 0; } } else if (ioh_valid) { sc->sc_st = iot; sc->sc_sh = ioh; psc->sc_mapsize = iosize; if (memh_valid) { bus_space_unmap(memt, memh, memsize); memh_valid = 0; } } else { aprint_error_dev(self, "unable to map device registers\n"); goto fail; } sc->sc_dmat = pa->pa_dmat; /* * Make sure bus mastering is enabled. */ pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | PCI_COMMAND_MASTER_ENABLE); /* * Get the cacheline size. */ sc->sc_cacheline = PCI_CACHELINE(pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG)); /* * Get PCI data moving command info. */ if (pa->pa_flags & PCI_FLAGS_MRL_OKAY) sc->sc_flags |= TULIPF_MRL; if (pa->pa_flags & PCI_FLAGS_MRM_OKAY) sc->sc_flags |= TULIPF_MRM; if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) sc->sc_flags |= TULIPF_MWI; /* * Read the contents of the Ethernet Address ROM/SROM. */ switch (sc->sc_chip) { case TULIP_CHIP_21040: sc->sc_srom_addrbits = 6; sc->sc_srom = malloc(TULIP_ROM_SIZE(6), M_DEVBUF, M_NOWAIT); TULIP_WRITE(sc, CSR_MIIROM, MIIROM_SROMCS); for (i = 0; i < TULIP_ROM_SIZE(6); i++) { for (j = 0; j < 10000; j++) { val = TULIP_READ(sc, CSR_MIIROM); if ((val & MIIROM_DN) == 0) break; } sc->sc_srom[i] = val & MIIROM_DATA; } break; case TULIP_CHIP_82C168: case TULIP_CHIP_82C169: { sc->sc_srom_addrbits = 2; sc->sc_srom = malloc(TULIP_ROM_SIZE(2), M_DEVBUF, M_NOWAIT); /* * The Lite-On PNIC stores the Ethernet address in * the first 3 words of the EEPROM. EEPROM access * is not like the other Tulip chips. */ for (i = 0; i < 6; i += 2) { TULIP_WRITE(sc, CSR_PNIC_SROMCTL, PNIC_SROMCTL_READ | (i >> 1)); for (j = 0; j < 500; j++) { delay(2); val = TULIP_READ(sc, CSR_MIIROM); if ((val & PNIC_MIIROM_BUSY) == 0) break; } if (val & PNIC_MIIROM_BUSY) { aprint_error_dev(self, "EEPROM timed out\n"); goto fail; } val &= PNIC_MIIROM_DATA; sc->sc_srom[i] = val >> 8; sc->sc_srom[i + 1] = val & 0xff; } break; } default: /* * XXX This isn't quite the right way to do this; we should * XXX be attempting to fetch the mac-addr property in the * XXX bus-agnostic part of the driver independently. But * XXX that requires a larger change in the SROM handling * XXX logic, and for now we can at least remove a machine- * XXX dependent wart from the PCI front-end. */ ea = prop_dictionary_get(device_properties(self), "mac-address"); if (ea != NULL) { extern int tlp_srom_debug; KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); sc->sc_srom_addrbits = 6; sc->sc_srom = malloc(TULIP_ROM_SIZE(6), M_DEVBUF, M_NOWAIT|M_ZERO); memcpy(sc->sc_srom, enaddr, sizeof(enaddr)); if (tlp_srom_debug) { aprint_normal("SROM CONTENTS:"); for (i = 0; i < TULIP_ROM_SIZE(6); i++) { if ((i % 8) == 0) aprint_normal("\n\t"); aprint_normal("0x%02x ", sc->sc_srom[i]); } aprint_normal("\n"); } break; } /* Check for a slaved ROM on a multi-port board. */ tlp_pci_check_slaved(psc, TULIP_PCI_SHAREDROM, TULIP_PCI_SLAVEROM); if (psc->sc_flags & TULIP_PCI_SLAVEROM) { sc->sc_srom_addrbits = psc->sc_master->sc_tulip.sc_srom_addrbits; sc->sc_srom = psc->sc_master->sc_tulip.sc_srom; enaddr[5] += sc->sc_devno - psc->sc_master->sc_tulip.sc_devno; } else if (tlp_read_srom(sc) == 0) goto cant_cope; break; } /* * Deal with chip/board quirks. This includes setting up * the mediasw, and extracting the Ethernet address from * the rombuf. */ switch (sc->sc_chip) { case TULIP_CHIP_21040: /* * Parse the Ethernet Address ROM. */ if (tlp_parse_old_srom(sc, enaddr) == 0) goto cant_cope; /* * All 21040 boards start out with the same * media switch. */ sc->sc_mediasw = &tlp_21040_mediasw; /* * Deal with any quirks this board might have. */ tlp_pci_get_quirks(psc, enaddr, tlp_pci_21040_quirks); break; case TULIP_CHIP_21041: /* Check for new format SROM. */ if (tlp_isv_srom_enaddr(sc, enaddr) == 0) { /* * Not an ISV SROM; try the old DEC Ethernet Address * ROM format. */ if (tlp_parse_old_srom(sc, enaddr) == 0) goto cant_cope; } /* * All 21041 boards use the same media switch; they all * work basically the same! Yippee! */ sc->sc_mediasw = &tlp_21041_mediasw; /* * Deal with any quirks this board might have. */ tlp_pci_get_quirks(psc, enaddr, tlp_pci_21041_quirks); break; case TULIP_CHIP_21140: case TULIP_CHIP_21140A: /* Check for new format SROM. */ if (tlp_isv_srom_enaddr(sc, enaddr) == 0) { /* * Not an ISV SROM; try the old DEC Ethernet Address * ROM format. */ if (tlp_parse_old_srom(sc, enaddr) == 0) goto cant_cope; } else { /* * We start out with the 2114x ISV media switch. * When we search for quirks, we may change to * a different switch. */ sc->sc_mediasw = &tlp_2114x_isv_mediasw; } /* * Deal with any quirks this board might have. */ tlp_pci_get_quirks(psc, enaddr, tlp_pci_21140_quirks); /* * Bail out now if we can't deal with this board. */ if (sc->sc_mediasw == NULL) goto cant_cope; break; case TULIP_CHIP_21142: case TULIP_CHIP_21143: /* Check for new format SROM. */ if (tlp_isv_srom_enaddr(sc, enaddr) == 0) { /* * Not an ISV SROM; try the old DEC Ethernet Address * ROM format. */ if (tlp_parse_old_srom(sc, enaddr) == 0) { /* * One last try: just copy the address * from offset 20 and try to look * up quirks. */ memcpy(enaddr, &sc->sc_srom[20], ETHER_ADDR_LEN); } } else { /* * We start out with the 2114x ISV media switch. * When we search for quirks, we may change to * a different switch. */ sc->sc_mediasw = &tlp_2114x_isv_mediasw; } /* * Deal with any quirks this board might have. */ tlp_pci_get_quirks(psc, enaddr, tlp_pci_21142_quirks); /* * Bail out now if we can't deal with this board. */ if (sc->sc_mediasw == NULL) goto cant_cope; break; case TULIP_CHIP_82C168: case TULIP_CHIP_82C169: /* * Lite-On PNIC's Ethernet address is the first 6 * bytes of its EEPROM. */ memcpy(enaddr, sc->sc_srom, ETHER_ADDR_LEN); /* * Lite-On PNICs always use the same mediasw; we * select MII vs. internal NWAY automatically. */ sc->sc_mediasw = &tlp_pnic_mediasw; break; case TULIP_CHIP_MX98713: /* * The Macronix MX98713 has an MII and GPIO, but no * internal Nway block. This chip is basically a * perfect 21140A clone, with the exception of the * a magic register frobbing in order to make the * interface function. */ if (tlp_isv_srom_enaddr(sc, enaddr)) { sc->sc_mediasw = &tlp_2114x_isv_mediasw; break; } /* FALLTHROUGH */ case TULIP_CHIP_82C115: /* * Yippee! The Lite-On 82C115 is a clone of * the MX98725 (the data sheet even says `MXIC' * on it)! Imagine that, a clone of a clone. * * The differences are really minimal: * * - Wake-On-LAN support * - 128-bit multicast hash table, rather than * the standard 512-bit hash table */ /* FALLTHROUGH */ case TULIP_CHIP_MX98713A: case TULIP_CHIP_MX98715A: case TULIP_CHIP_MX98715AEC_X: case TULIP_CHIP_MX98725: /* * The MX98713A has an MII as well as an internal Nway block, * but no GPIO. The MX98715 and MX98725 have an internal * Nway block only. * * The internal Nway block, unlike the Lite-On PNIC's, does * just that - performs Nway. Once autonegotiation completes, * we must program the GPR media information into the chip. * * The byte offset of the Ethernet address is stored at * offset 0x70. */ memcpy(enaddr, &sc->sc_srom[sc->sc_srom[0x70]], ETHER_ADDR_LEN); sc->sc_mediasw = &tlp_pmac_mediasw; break; case TULIP_CHIP_WB89C840F: /* * Winbond 89C840F's Ethernet address is the first * 6 bytes of its EEPROM. */ memcpy(enaddr, sc->sc_srom, ETHER_ADDR_LEN); /* * Winbond 89C840F has an MII attached to the SIO. */ sc->sc_mediasw = &tlp_sio_mii_mediasw; break; case TULIP_CHIP_AL981: /* * The ADMtek AL981's Ethernet address is located * at offset 8 of its EEPROM. */ memcpy(enaddr, &sc->sc_srom[8], ETHER_ADDR_LEN); /* * ADMtek AL981 has a built-in PHY accessed through * special registers. */ sc->sc_mediasw = &tlp_al981_mediasw; break; case TULIP_CHIP_AN983: case TULIP_CHIP_AN985: /* * The ADMtek AN985's Ethernet address is located * at offset 8 of its EEPROM. */ memcpy(enaddr, &sc->sc_srom[8], ETHER_ADDR_LEN); /* * The ADMtek AN985 can be configured in Single-Chip * mode or MAC-only mode. Single-Chip uses the built-in * PHY, MAC-only has an external PHY (usually HomePNA). * The selection is based on an EEPROM setting, and both * PHYs are accessed via MII attached to SIO. * * The AN985 "ghosts" the internal PHY onto all * MII addresses, so we have to use a media init * routine that limits the search. * XXX How does this work with MAC-only mode? */ sc->sc_mediasw = &tlp_an985_mediasw; break; case TULIP_CHIP_DM9102: case TULIP_CHIP_DM9102A: /* * Some boards with the Davicom chip have an ISV * SROM (mostly DM9102A boards -- trying to describe * the HomePNA PHY, probably) although the data in * them is generally wrong. Check for ISV format * and grab the Ethernet address that way, and if * that fails, fall back on grabbing it from an * observed offset of 20 (which is where it would * be in an ISV SROM anyhow, tho ISV can cope with * multi-port boards). */ if (!tlp_isv_srom_enaddr(sc, enaddr)) { prop_data_t eaddrprop; eaddrprop = prop_dictionary_get( device_properties(self), "mac-address"); if (eaddrprop != NULL && prop_data_size(eaddrprop) == ETHER_ADDR_LEN) memcpy(enaddr, prop_data_data_nocopy(eaddrprop), ETHER_ADDR_LEN); else memcpy(enaddr, &sc->sc_srom[20], ETHER_ADDR_LEN); } /* * Davicom chips all have an internal MII interface * and a built-in PHY. DM9102A also has a an external * MII interface, usually with a HomePNA PHY attached * to it. */ sc->sc_mediasw = &tlp_dm9102_mediasw; break; case TULIP_CHIP_AX88140: case TULIP_CHIP_AX88141: /* * ASIX AX88140/AX88141 Ethernet Address is located at offset * 20 of the SROM. */ memcpy(enaddr, &sc->sc_srom[20], ETHER_ADDR_LEN); /* * ASIX AX88140A/AX88141 chip can have a built-in PHY or * an external MII interface. */ sc->sc_mediasw = &tlp_asix_mediasw; break; case TULIP_CHIP_RS7112: /* * RS7112 Ethernet Address is located of offset 0x19a * of the SROM */ memcpy(enaddr, &sc->sc_srom[0x19a], ETHER_ADDR_LEN); /* RS7112 chip has a PHY at MII address 1 */ sc->sc_mediasw = &tlp_rs7112_mediasw; break; default: cant_cope: aprint_error_dev(self, "sorry, unable to handle your board\n"); goto fail; } /* * Handle shared interrupts. */ if (psc->sc_flags & TULIP_PCI_SHAREDINTR) { if (psc->sc_master) psc->sc_flags |= TULIP_PCI_SLAVEINTR; else { tlp_pci_check_slaved(psc, TULIP_PCI_SHAREDINTR, TULIP_PCI_SLAVEINTR); if (psc->sc_master == NULL) psc->sc_master = psc; } LIST_INSERT_HEAD(&psc->sc_master->sc_intrslaves, psc, sc_intrq); } if (psc->sc_flags & TULIP_PCI_SLAVEINTR) { aprint_normal_dev(self, "sharing interrupt with %s\n", device_xname(psc->sc_master->sc_tulip.sc_dev)); } else { /* * Map and establish our interrupt. */ if (pci_intr_map(pa, &ih)) { aprint_error_dev(self, "unable to map interrupt\n"); goto fail; } intrstr = pci_intr_string(pc, ih); psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, (psc->sc_flags & TULIP_PCI_SHAREDINTR) ? tlp_pci_shared_intr : tlp_intr, sc); if (psc->sc_ih == NULL) { aprint_error_dev(self, "unable to establish interrupt"); if (intrstr != NULL) aprint_error(" at %s", intrstr); aprint_error("\n"); goto fail; } aprint_normal_dev(self, "interrupting at %s\n", intrstr); } /* * Finish off the attach. */ error = tlp_attach(sc, enaddr); if (error) goto fail; return; fail: if (psc->sc_ih != NULL) { pci_intr_disestablish(psc->sc_pc, psc->sc_ih); psc->sc_ih = NULL; } if (ioh_valid) bus_space_unmap(iot, ioh, iosize); if (memh_valid) bus_space_unmap(memt, memh, memsize); psc->sc_mapsize = 0; return; }
static void atw_pci_attach(device_t parent, device_t self, void *aux) { struct atw_pci_softc *psc = device_private(self); struct atw_softc *sc = &psc->psc_atw; struct pci_attach_args *pa = aux; pci_chipset_tag_t pc = pa->pa_pc; const char *intrstr = NULL; bus_space_tag_t iot, memt; bus_space_handle_t ioh, memh; int ioh_valid, memh_valid; const struct atw_pci_product *app; int error; sc->sc_dev = self; psc->psc_pc = pa->pa_pc; psc->psc_pcitag = pa->pa_tag; app = atw_pci_lookup(pa); if (app == NULL) { printf("\n"); panic("atw_pci_attach: impossible"); } /* * Get revision info, and set some chip-specific variables. */ sc->sc_rev = PCI_REVISION(pa->pa_class); printf(": %s, revision %d.%d\n", app->app_product_name, (sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf); /* power up chip */ if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && error != EOPNOTSUPP) { aprint_error_dev(self, "cannot activate %d\n", error); return; } /* * Map the device. */ ioh_valid = (pci_mapreg_map(pa, ATW_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL) == 0); memh_valid = (pci_mapreg_map(pa, ATW_PCI_MMBA, PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, NULL, NULL) == 0); if (memh_valid) { sc->sc_st = memt; sc->sc_sh = memh; } else if (ioh_valid) { sc->sc_st = iot; sc->sc_sh = ioh; } else { printf(": unable to map device registers\n"); return; } sc->sc_dmat = pa->pa_dmat; /* * Make sure bus mastering is enabled. */ pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | PCI_COMMAND_MASTER_ENABLE); /* * Get the cacheline size. */ sc->sc_cacheline = PCI_CACHELINE(pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG)); /* * Get PCI data moving command info. */ if (pa->pa_flags & PCI_FLAGS_MRL_OKAY) /* read line */ sc->sc_flags |= ATWF_MRL; if (pa->pa_flags & PCI_FLAGS_MRM_OKAY) /* read multiple */ sc->sc_flags |= ATWF_MRM; if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) /* write invalidate */ sc->sc_flags |= ATWF_MWI; /* * Map and establish our interrupt. */ if (pci_intr_map(pa, &psc->psc_ih)) { aprint_error_dev(self, "unable to map interrupt\n"); return; } intrstr = pci_intr_string(pc, psc->psc_ih); psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET, atw_intr, sc); if (psc->psc_intrcookie == NULL) { aprint_error_dev(self, "unable to establish interrupt"); if (intrstr != NULL) aprint_error(" at %s", intrstr); aprint_error("\n"); return; } aprint_normal_dev(self, "interrupting at %s\n", intrstr); /* * Bus-independent attach. */ atw_attach(sc); if (pmf_device_register1(sc->sc_dev, atw_pci_suspend, atw_pci_resume, atw_shutdown)) pmf_class_network_register(sc->sc_dev, &sc->sc_if); else aprint_error_dev(sc->sc_dev, "couldn't establish power handler\n"); /* * Power down the socket. */ pmf_device_suspend(sc->sc_dev, &sc->sc_qual); }