/**
* Applies relocations to data and code managed by this component.
*
* This function will be called at init and whenever the VMM need to relocate
* itself inside the GC.
*
* @param pVM Pointer to the VM.
* @param offDelta Relocation delta relative to old location.
*/
VMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta)
{
#if 0
int rc = PDMR3LdrGetSymbolRC(pVM, NULL /* pszModule */, GIMHV_HYPERCALL, &pVM->gim.s.pfnHypercallRC);
AssertFatalRC(rc);
#endif
}
VMMR3_INT_DECL(int) gimR3HvInitFinalize(PVM pVM)
{
pVM->gim.s.pfnHypercallR3 = &GIMHvHypercall;
if (!HMIsEnabled(pVM))
{
rc = PDMR3LdrGetSymbolRC(pVM, NULL /* pszModule */, GIMHV_HYPERCALL, &pVM->gim.s.pfnHypercallRC);
AssertRCReturn(rc, rc);
}
rc = PDMR3LdrGetSymbolR0(pVM, NULL /* pszModule */, GIMHV_HYPERCALL, &pVM->gim.s.pfnHypercallR0);
AssertRCReturn(rc, rc);
}
/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetRCHelpers} */
static DECLCALLBACK(PCPDMPCIRAWHLPRC) pdmR3PciRawHlp_GetRCHelpers(PPDMDEVINS pDevIns)
{
PDMDEV_ASSERT_DEVINS(pDevIns);
VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
RTRCPTR pRCHelpers = NIL_RTRCPTR;
int rc = PDMR3LdrGetSymbolRC(pDevIns->Internal.s.pVMR3, NULL, "g_pdmRCPciRawHlp", &pRCHelpers);
AssertReleaseRC(rc);
AssertRelease(pRCHelpers);
LogFlow(("pdmR3PciRawHlp_GetGCHelpers: caller='%s'/%d: returns %RRv\n",
pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
return pRCHelpers;
}
/** @interface_method_impl{PDMPICHLPR3,pfnGetRCHelpers} */
static DECLCALLBACK(PCPDMPICHLPRC) pdmR3PicHlp_GetRCHelpers(PPDMDEVINS pDevIns)
{
PDMDEV_ASSERT_DEVINS(pDevIns);
PVM pVM = pDevIns->Internal.s.pVMR3;
VM_ASSERT_EMT(pVM);
RTRCPTR pRCHelpers = NIL_RTRCPTR;
if (!HMIsEnabled(pVM))
{
int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPicHlp", &pRCHelpers);
AssertReleaseRC(rc);
AssertRelease(pRCHelpers);
}
LogFlow(("pdmR3PicHlp_GetRCHelpers: caller='%s'/%d: returns %RRv\n",
pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
return pRCHelpers;
}
/**
* Performs a testcase.
*
* @returns return value from the test.
* @param pVM Pointer to the VM.
* @param enmTestcase The testcase operation to perform.
* @param uVariation The testcase variation id.
*/
static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
{
PVMCPU pVCpu = &pVM->aCpus[0];
RTRCPTR RCPtrEP;
int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
if (RT_FAILURE(rc))
return rc;
Log(("vmmR3DoGCTest: %d %#x\n", enmTestcase, uVariation));
CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
vmmR3TestClearStack(pVCpu);
CPUMPushHyper(pVCpu, uVariation);
CPUMPushHyper(pVCpu, enmTestcase);
CPUMPushHyper(pVCpu, pVM->pVMRC);
CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
#if 1
/* flush the raw-mode logs. */
# ifdef LOG_ENABLED
PRTLOGGERRC pLogger = pVM->vmm.s.pRCLoggerR3;
if ( pLogger
&& pLogger->offScratch > 0)
RTLogFlushRC(NULL, pLogger);
# endif
# ifdef VBOX_WITH_RC_RELEASE_LOGGING
PRTLOGGERRC pRelLogger = pVM->vmm.s.pRCRelLoggerR3;
if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
RTLogFlushRC(RTLogRelDefaultInstance(), pRelLogger);
# endif
#endif
Log(("vmmR3DoGCTest: rc=%Rrc iLastGZRc=%Rrc\n", rc, pVCpu->vmm.s.iLastGZRc));
if (RT_LIKELY(rc == VINF_SUCCESS))
rc = pVCpu->vmm.s.iLastGZRc;
return rc;
}
/**
* Performs a testcase.
*
* @returns return value from the test.
* @param pVM Pointer to the VM.
* @param enmTestcase The testcase operation to perform.
* @param uVariation The testcase variation id.
*/
static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
{
PVMCPU pVCpu = &pVM->aCpus[0];
RTRCPTR RCPtrEP;
int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
if (RT_FAILURE(rc))
return rc;
CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
vmmR3TestClearStack(pVCpu);
CPUMPushHyper(pVCpu, uVariation);
CPUMPushHyper(pVCpu, enmTestcase);
CPUMPushHyper(pVCpu, pVM->pVMRC);
CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
if (RT_LIKELY(rc == VINF_SUCCESS))
rc = pVCpu->vmm.s.iLastGZRc;
return rc;
}
/** @interface_method_impl{PDMDEVREG,pfnConstruct} */
static DECLCALLBACK(int) ox958R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
{
RT_NOREF(iInstance);
PDEVOX958 pThis = PDMINS_2_DATA(pDevIns, PDEVOX958);
bool fRCEnabled = true;
bool fR0Enabled = true;
bool fMsiXSupported = false;
int rc;
PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
/*
* Validate and read configuration.
*/
if (!CFGMR3AreValuesValid(pCfg, "RCEnabled\0"
"R0Enabled\0"
"MsiXSupported\0"
"UartCount\0"))
return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
N_("OXPCIe958 configuration error: Unknown option specified"));
rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &fRCEnabled, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("OXPCIe958 configuration error: Failed to read \"RCEnabled\" as boolean"));
rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("OXPCIe958 configuration error: failed to read \"R0Enabled\" as boolean"));
rc = CFGMR3QueryBoolDef(pCfg, "MsiXSupported", &fMsiXSupported, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("OXPCIe958 configuration error: failed to read \"MsiXSupported\" as boolean"));
rc = CFGMR3QueryU32Def(pCfg, "UartCount", &pThis->cUarts, OX958_UARTS_MAX);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("OXPCIe958 configuration error: failed to read \"UartCount\" as unsigned 32bit integer"));
if (!pThis->cUarts || pThis->cUarts > OX958_UARTS_MAX)
return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
N_("OXPCIe958 configuration error: \"UartCount\" has invalid value %u (must be in range [1 .. %u]"),
pThis->cUarts, OX958_UARTS_MAX);
/*
* Init instance data.
*/
pThis->fR0Enabled = fR0Enabled;
pThis->fRCEnabled = fRCEnabled;
pThis->pDevInsR3 = pDevIns;
pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
/* Fill PCI config space. */
PDMPciDevSetVendorId (&pThis->PciDev, OX958_PCI_VENDOR_ID);
PDMPciDevSetDeviceId (&pThis->PciDev, OX958_PCI_DEVICE_ID);
PDMPciDevSetCommand (&pThis->PciDev, 0x0000);
#ifdef VBOX_WITH_MSI_DEVICES
PDMPciDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST);
PDMPciDevSetCapabilityList (&pThis->PciDev, OX958_PCI_MSI_CAP_OFS);
#else
PDMPciDevSetCapabilityList (&pThis->PciDev, 0x70);
#endif
PDMPciDevSetRevisionId (&pThis->PciDev, 0x00);
PDMPciDevSetClassBase (&pThis->PciDev, 0x07); /* Communication controller. */
PDMPciDevSetClassSub (&pThis->PciDev, 0x00); /* Serial controller. */
PDMPciDevSetClassProg (&pThis->PciDev, 0x02); /* 16550. */
PDMPciDevSetRevisionId (&pThis->PciDev, 0x00);
PDMPciDevSetSubSystemVendorId(&pThis->PciDev, OX958_PCI_VENDOR_ID);
PDMPciDevSetSubSystemId (&pThis->PciDev, OX958_PCI_DEVICE_ID);
PDMPciDevSetInterruptLine (&pThis->PciDev, 0x00);
PDMPciDevSetInterruptPin (&pThis->PciDev, 0x01);
/** @todo More Capabilities. */
rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
if (RT_FAILURE(rc))
return rc;
/*
* Register PCI device and I/O region.
*/
rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
if (RT_FAILURE(rc))
return rc;
#ifdef VBOX_WITH_MSI_DEVICES
PDMMSIREG MsiReg;
RT_ZERO(MsiReg);
MsiReg.cMsiVectors = 1;
MsiReg.iMsiCapOffset = OX958_PCI_MSI_CAP_OFS;
MsiReg.iMsiNextOffset = OX958_PCI_MSIX_CAP_OFS;
MsiReg.fMsi64bit = true;
if (fMsiXSupported)
{
MsiReg.cMsixVectors = VBOX_MSIX_MAX_ENTRIES;
MsiReg.iMsixCapOffset = OX958_PCI_MSIX_CAP_OFS;
MsiReg.iMsixNextOffset = 0x00;
MsiReg.iMsixBar = OX958_PCI_MSIX_BAR;
}
rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
if (RT_FAILURE(rc))
{
PCIDevSetCapabilityList(&pThis->PciDev, 0x0);
/* That's OK, we can work without MSI */
}
#endif
rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, _16K, PCI_ADDRESS_SPACE_MEM, ox958R3Map);
if (RT_FAILURE(rc))
return rc;
PVM pVM = PDMDevHlpGetVM(pDevIns);
RTR0PTR pfnSerialIrqReqR0 = NIL_RTR0PTR;
RTRCPTR pfnSerialIrqReqRC = NIL_RTRCPTR;
if ( fRCEnabled
&& VM_IS_RAW_MODE_ENABLED(pVM))
{
rc = PDMR3LdrGetSymbolRC(pVM, pDevIns->pReg->szRCMod, "ox958IrqReq", &pfnSerialIrqReqRC);
if (RT_FAILURE(rc))
return rc;
}
if (fR0Enabled)
{
rc = PDMR3LdrGetSymbolR0(pVM, pDevIns->pReg->szR0Mod, "ox958IrqReq", &pfnSerialIrqReqR0);
if (RT_FAILURE(rc))
return rc;
}
for (uint32_t i = 0; i < pThis->cUarts; i++)
{
POX958UART pUart = &pThis->aUarts[i];
rc = uartR3Init(&pUart->UartCore, pDevIns, UARTTYPE_16550A, i, 0, ox958IrqReq, pfnSerialIrqReqR0, pfnSerialIrqReqRC);
if (RT_FAILURE(rc))
return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
N_("OXPCIe958 configuration error: failed to initialize UART %u"), i);
}
ox958R3Reset(pDevIns);
return VINF_SUCCESS;
}
static DECLCALLBACK(int) doit(PVM pVM)
{
RTPrintf(TESTCASE ": testing...\n");
SetupSelectors(pVM);
/*
* Loading the module and resolve the entry point.
*/
int rc = PDMR3LdrLoadRC(pVM, NULL, "tstMicroRC.gc");
if (RT_FAILURE(rc))
{
RTPrintf(TESTCASE ": Failed to load tstMicroRC.gc, rc=%Rra\n", rc);
return rc;
}
RTRCPTR RCPtrEntry;
rc = PDMR3LdrGetSymbolRC(pVM, "tstMicroRC.gc", "tstMicroRC", &RCPtrEntry);
if (RT_FAILURE(rc))
{
RTPrintf(TESTCASE ": Failed to resolve the 'tstMicroRC' entry point in tstMicroRC.gc, rc=%Rra\n", rc);
return rc;
}
RTRCPTR RCPtrStart;
rc = PDMR3LdrGetSymbolRC(pVM, "tstMicroRC.gc", "tstMicroRCAsmStart", &RCPtrStart);
if (RT_FAILURE(rc))
{
RTPrintf(TESTCASE ": Failed to resolve the 'tstMicroRCAsmStart' entry point in tstMicroRC.gc, rc=%Rra\n", rc);
return rc;
}
RTRCPTR RCPtrEnd;
rc = PDMR3LdrGetSymbolRC(pVM, "tstMicroRC.gc", "tstMicroRCAsmEnd", &RCPtrEnd);
if (RT_FAILURE(rc))
{
RTPrintf(TESTCASE ": Failed to resolve the 'tstMicroRCAsmEnd' entry point in tstMicroRC.gc, rc=%Rra\n", rc);
return rc;
}
/*
* Allocate and initialize the instance data.
*/
PTSTMICRO pTst;
rc = MMHyperAlloc(pVM, RT_ALIGN_Z(sizeof(*pTst), PAGE_SIZE), PAGE_SIZE, MM_TAG_VM, (void **)&pTst);
if (RT_FAILURE(rc))
{
RTPrintf(TESTCASE ": Failed to resolve allocate instance memory (%d bytes), rc=%Rra\n", sizeof(*pTst), rc);
return rc;
}
pTst->RCPtr = MMHyperR3ToRC(pVM, pTst);
pTst->RCPtrStack = MMHyperR3ToRC(pVM, &pTst->au8Stack[sizeof(pTst->au8Stack) - 32]);
/* the page must be writable from user mode */
rc = PGMMapModifyPage(pVM, pTst->RCPtr, sizeof(*pTst), X86_PTE_US | X86_PTE_RW, ~(uint64_t)(X86_PTE_US | X86_PTE_RW));
if (RT_FAILURE(rc))
{
RTPrintf(TESTCASE ": PGMMapModifyPage -> rc=%Rra\n", rc);
return rc;
}
/* all the code must be executable from R3. */
rc = PGMMapModifyPage(pVM, RCPtrStart, RCPtrEnd - RCPtrStart + PAGE_SIZE, X86_PTE_US, ~(uint64_t)X86_PTE_US);
if (RT_FAILURE(rc))
{
RTPrintf(TESTCASE ": PGMMapModifyPage -> rc=%Rra\n", rc);
return rc;
}
DBGFR3PagingDumpEx(pVM->pUVM, 0 /*idCpu*/, DBGFPGDMP_FLAGS_CURRENT_CR3 | DBGFPGDMP_FLAGS_CURRENT_MODE
| DBGFPGDMP_FLAGS_SHADOW | DBGFPGDMP_FLAGS_HEADER | DBGFPGDMP_FLAGS_PRINT_CR3,
0 /*cr3*/, 0 /*u64FirstAddr*/, UINT64_MAX /*u64LastAddr*/, 99 /*cMaxDepth*/, NULL);
#if 0
/*
* Disassemble the assembly...
*/
RTGCPTR GCPtr = RCPtrStart;
while (GCPtr < RCPtrEnd)
{
size_t cb = 0;
char sz[256];
int rc = DBGFR3DisasInstrEx(pVM, CPUMGetHyperCS(pVM), GCPtr, 0, sz, sizeof(sz), &cb);
if (RT_SUCCESS(rc))
RTLogPrintf("%s\n", sz);
else
{
RTLogPrintf("%RGv rc=%Rrc\n", GCPtr, rc);
cb = 1;
}
GCPtr += cb;
}
#endif
#ifdef VBOX_WITH_RAW_MODE
/*
* Do the profiling.
*/
/* execute the instruction profiling tests */
PrintHeaderInstr();
int i;
for (i = TSTMICROTEST_OVERHEAD; i < TSTMICROTEST_TRAP_FIRST; i++)
{
TSTMICROTEST enmTest = (TSTMICROTEST)i;
uint64_t cMin = ~0;
uint64_t cMax = 0;
uint64_t cTotal = 0;
unsigned cSamples = 0;
rc = VINF_SUCCESS;
for (int c = 0; c < 100; c++)
{
int rc2 = VMMR3CallRC(pVM, RCPtrEntry, 2, pTst->RCPtr, enmTest);
if (RT_SUCCESS(rc2))
{
uint64_t u64 = pTst->aResults[enmTest].cTotalTicks;
if (cMin > u64)
cMin = u64;
if (cMax < u64)
cMax = u64;
cTotal += u64;
cSamples++;
}
else if (RT_SUCCESS(rc))
rc = rc2;
}
uint64_t cAvg = cTotal / (cSamples ? cSamples : 1);
pTst->aResults[enmTest].cTotalTicks = cAvg;
PrintResultInstr(pTst, enmTest, rc, cMin, cAvg, cMax);
/* store the overhead */
if (enmTest == TSTMICROTEST_OVERHEAD)
pTst->u64Overhead = cMin;
}
#endif
#ifdef VBOX_WITH_RAW_MODE
/* execute the trap/cycle profiling tests. */
RTPrintf("\n");
PrintHeaderTraps();
/* don't disable rdtsc in R1/R2/R3! */
CPUMR3SetCR4Feature(pVM, 0, ~X86_CR4_TSD);
for (i = TSTMICROTEST_TRAP_FIRST; i < TSTMICROTEST_MAX; i++)
{
TSTMICROTEST enmTest = (TSTMICROTEST)i;
rc = VMMR3CallRC(pVM, RCPtrEntry, 2, pTst->RCPtr, enmTest);
PrintResultTrap(pTst, enmTest, rc);
}
#endif
RTPrintf(TESTCASE ": done!\n");
return VINF_SUCCESS;
}
/**
* Performs a trap test.
*
* @returns Return value from the trap test.
* @param pVM Pointer to the VM.
* @param u8Trap The trap number to test.
* @param uVariation The testcase variation.
* @param rcExpect The expected result.
* @param u32Eax The expected eax value.
* @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
* @param pszDesc The test description.
*/
static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
{
PVMCPU pVCpu = &pVM->aCpus[0];
RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
RTRCPTR RCPtrEP;
int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
if (RT_FAILURE(rc))
return rc;
CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
vmmR3TestClearStack(pVCpu);
CPUMPushHyper(pVCpu, uVariation);
CPUMPushHyper(pVCpu, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
CPUMPushHyper(pVCpu, pVM->pVMRC);
CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
if (RT_LIKELY(rc == VINF_SUCCESS))
rc = pVCpu->vmm.s.iLastGZRc;
bool fDump = false;
if (rc != rcExpect)
{
RTPrintf("VMM: FAILURE - rc=%Rrc expected %Rrc\n", rc, rcExpect);
if (rc != VERR_NOT_IMPLEMENTED)
fDump = true;
}
else if ( rcExpect != VINF_SUCCESS
&& u8Trap != 8 /* double fault doesn't dare set TrapNo. */
&& u8Trap != 3 /* guest only, we're not in guest. */
&& u8Trap != 1 /* guest only, we're not in guest. */
&& u8Trap != TRPMGetTrapNo(pVCpu))
{
RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVCpu), u8Trap);
fDump = true;
}
else if (pszFaultEIP)
{
RTRCPTR RCPtrFault;
int rc2 = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &RCPtrFault);
if (RT_FAILURE(rc2))
RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Rrc!\n", pszFaultEIP, rc);
else if (RCPtrFault != CPUMGetHyperEIP(pVCpu))
{
RTPrintf("VMM: FAILURE - EIP=%08RX32 expected %RRv (%s)\n", CPUMGetHyperEIP(pVCpu), RCPtrFault, pszFaultEIP);
fDump = true;
}
}
else if (rcExpect != VINF_SUCCESS)
{
if (CPUMGetHyperSS(pVCpu) == SELMGetHyperDS(pVM))
RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVCpu), SELMGetHyperDS(pVM));
if (CPUMGetHyperES(pVCpu) == SELMGetHyperDS(pVM))
RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVCpu), SELMGetHyperDS(pVM));
if (CPUMGetHyperDS(pVCpu) == SELMGetHyperDS(pVM))
RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVCpu), SELMGetHyperDS(pVM));
if (CPUMGetHyperFS(pVCpu) == SELMGetHyperDS(pVM))
RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVCpu), SELMGetHyperDS(pVM));
if (CPUMGetHyperGS(pVCpu) == SELMGetHyperDS(pVM))
RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVCpu), SELMGetHyperDS(pVM));
if (CPUMGetHyperEDI(pVCpu) == 0x01234567)
RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVCpu), 0x01234567);
if (CPUMGetHyperESI(pVCpu) == 0x42000042)
RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVCpu), 0x42000042);
if (CPUMGetHyperEBP(pVCpu) == 0xffeeddcc)
RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVCpu), 0xffeeddcc);
if (CPUMGetHyperEBX(pVCpu) == 0x89abcdef)
RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVCpu), 0x89abcdef);
if (CPUMGetHyperECX(pVCpu) == 0xffffaaaa)
RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVCpu), 0xffffaaaa);
if (CPUMGetHyperEDX(pVCpu) == 0x77778888)
RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVCpu), 0x77778888);
if (CPUMGetHyperEAX(pVCpu) == u32Eax)
RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVCpu), u32Eax);
}
if (fDump)
VMMR3FatalDump(pVM, pVCpu, rc);
return rc;
}
/* execute the switch. */
VMMR3DECL(int) VMMDoHwAccmTest(PVM pVM)
{
uint32_t i;
int rc;
PCPUMCTX pHyperCtx, pGuestCtx;
RTGCPHYS CR3Phys = 0x0; /* fake address */
PVMCPU pVCpu = &pVM->aCpus[0];
if (!HWACCMR3IsAllowed(pVM))
{
RTPrintf("VMM: Hardware accelerated test not available!\n");
return VERR_ACCESS_DENIED;
}
/*
* These forced actions are not necessary for the test and trigger breakpoints too.
*/
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
/* Enable mapping of the hypervisor into the shadow page table. */
uint32_t cb;
rc = PGMR3MappingsSize(pVM, &cb);
AssertRCReturn(rc, rc);
/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
AssertRCReturn(rc, rc);
pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
pHyperCtx->cr0 = X86_CR0_PE | X86_CR0_WP | X86_CR0_PG | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
pHyperCtx->cr4 = X86_CR4_PGE | X86_CR4_OSFSXR | X86_CR4_OSXMMEEXCPT;
PGMChangeMode(pVCpu, pHyperCtx->cr0, pHyperCtx->cr4, pHyperCtx->msrEFER);
PGMSyncCR3(pVCpu, pHyperCtx->cr0, CR3Phys, pHyperCtx->cr4, true);
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
VM_FF_CLEAR(pVM, VM_FF_REQUEST);
/*
* Setup stack for calling VMMGCEntry().
*/
RTRCPTR RCPtrEP;
rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
if (RT_SUCCESS(rc))
{
RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
/* Fill in hidden selector registers for the hypervisor state. */
SYNC_SEL(pHyperCtx, cs);
SYNC_SEL(pHyperCtx, ds);
SYNC_SEL(pHyperCtx, es);
SYNC_SEL(pHyperCtx, fs);
SYNC_SEL(pHyperCtx, gs);
SYNC_SEL(pHyperCtx, ss);
SYNC_SEL(pHyperCtx, tr);
/*
* Profile switching.
*/
RTPrintf("VMM: profiling switcher...\n");
Log(("VMM: profiling switcher...\n"));
uint64_t TickMin = ~0;
uint64_t tsBegin = RTTimeNanoTS();
uint64_t TickStart = ASMReadTSC();
for (i = 0; i < 1000000; i++)
{
CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
CPUMPushHyper(pVCpu, 0);
CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HWACCM_NOP);
CPUMPushHyper(pVCpu, pVM->pVMRC);
CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
pGuestCtx = CPUMQueryGuestCtxPtr(pVCpu);
/* Copy the hypervisor context to make sure we have a valid guest context. */
*pGuestCtx = *pHyperCtx;
pGuestCtx->cr3 = CR3Phys;
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
uint64_t TickThisStart = ASMReadTSC();
rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN, 0);
uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
if (RT_FAILURE(rc))
{
Log(("VMM: R0 returned fatal %Rrc in iteration %d\n", rc, i));
VMMR3FatalDump(pVM, pVCpu, rc);
return rc;
}
if (TickThisElapsed < TickMin)
TickMin = TickThisElapsed;
}
uint64_t TickEnd = ASMReadTSC();
uint64_t tsEnd = RTTimeNanoTS();
uint64_t Elapsed = tsEnd - tsBegin;
uint64_t PerIteration = Elapsed / (uint64_t)i;
uint64_t cTicksElapsed = TickEnd - TickStart;
uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
rc = VINF_SUCCESS;
}
else
AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
return rc;
}
/* execute the switch. */
VMMR3DECL(int) VMMDoTest(PVM pVM)
{
#if 1
PVMCPU pVCpu = &pVM->aCpus[0];
#ifdef NO_SUPCALLR0VMM
RTPrintf("NO_SUPCALLR0VMM\n");
return VINF_SUCCESS;
#endif
/*
* Setup stack for calling VMMGCEntry().
*/
RTRCPTR RCPtrEP;
int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
if (RT_SUCCESS(rc))
{
RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
/*
* Test various crashes which we must be able to recover from.
*/
vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
#if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
bool f;
rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
#if !defined(DEBUG_bird)
if (RT_SUCCESS(rc) && f)
#endif
{
/* see triple fault warnings in SELM and VMMGC.cpp. */
vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
}
#endif
vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
//vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
vmmR3DoTrapTest(pVM, 0xe, 2, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler");
/* This test is no longer relevant as fs and gs are loaded with NULL
selectors and we will always return to HC if a #GP occurs while
returning to guest code.
vmmR3DoTrapTest(pVM, 0xe, 4, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler and bad fs");
*/
/*
* Set a debug register and perform a context switch.
*/
rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
if (rc != VINF_SUCCESS)
{
RTPrintf("VMM: Nop test failed, rc=%Rrc not VINF_SUCCESS\n", rc);
return rc;
}
/* a harmless breakpoint */
RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
DBGFADDRESS Addr;
DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
RTUINT iBp0;
rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
AssertReleaseRC(rc);
rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
if (rc != VINF_SUCCESS)
{
RTPrintf("VMM: DR0=0x10000 test failed with rc=%Rrc!\n", rc);
return rc;
}
/* a bad one at VMMGCEntry */
RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
DBGFR3AddrFromFlat(pVM, &Addr, RCPtrEP);
RTUINT iBp1;
rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
AssertReleaseRC(rc);
rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
{
RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
return rc;
}
/* resume the breakpoint */
RTPrintf("VMM: resuming hyper after breakpoint\n");
CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
rc = VMMR3ResumeHyper(pVM, pVCpu);
if (rc != VINF_SUCCESS)
{
RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Rrc = KNOWN BUG\n", rc); /** @todo fix VMMR3ResumeHyper */
return rc;
}
/* engage the breakpoint again and try single stepping. */
RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
{
RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
return rc;
}
RTGCUINTREG OldPc = CPUMGetHyperEIP(pVCpu);
RTPrintf("%RGr=>", OldPc);
unsigned i;
for (i = 0; i < 8; i++)
{
CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
rc = VMMR3ResumeHyper(pVM, pVCpu);
if (rc != VINF_EM_DBG_HYPER_STEPPED)
{
RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Rrc\n", rc);
return rc;
}
RTGCUINTREG Pc = CPUMGetHyperEIP(pVCpu);
RTPrintf("%RGr=>", Pc);
if (Pc == OldPc)
{
RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
return VERR_GENERAL_FAILURE;
}
OldPc = Pc;
}
RTPrintf("ok\n");
/* done, clear it */
if ( RT_FAILURE(DBGFR3BpClear(pVM, iBp0))
|| RT_FAILURE(DBGFR3BpClear(pVM, iBp1)))
{
RTPrintf("VMM: Failed to clear breakpoints!\n");
return VERR_GENERAL_FAILURE;
}
rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
if (rc != VINF_SUCCESS)
{
RTPrintf("VMM: NOP failed, rc=%Rrc\n", rc);
return rc;
}
/*
* Interrupt masking.
*/
RTPrintf("VMM: interrupt masking...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
for (i = 0; i < 10000; i++)
{
uint64_t StartTick = ASMReadTSC();
rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_INTERRUPT_MASKING, 0);
if (rc != VINF_SUCCESS)
{
RTPrintf("VMM: Interrupt masking failed: rc=%Rrc\n", rc);
return rc;
}
uint64_t Ticks = ASMReadTSC() - StartTick;
if (Ticks < (SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000))
RTPrintf("Warning: Ticks=%RU64 (< %RU64)\n", Ticks, SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000);
}
/*
* Interrupt forwarding.
*/
CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
CPUMPushHyper(pVCpu, 0);
CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
CPUMPushHyper(pVCpu, pVM->pVMRC);
CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
Log(("trampoline=%x\n", pVM->vmm.s.pfnCallTrampolineRC));
/*
* Switch and do da thing.
*/
RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
i = 0;
uint64_t tsBegin = RTTimeNanoTS();
uint64_t TickStart = ASMReadTSC();
Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
do
{
rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
if (RT_LIKELY(rc == VINF_SUCCESS))
rc = pVCpu->vmm.s.iLastGZRc;
if (RT_FAILURE(rc))
{
Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
VMMR3FatalDump(pVM, pVCpu, rc);
return rc;
}
i++;
if (!(i % 32))
Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
i, CPUMGetHyperESI(pVCpu), CPUMGetHyperEDI(pVCpu), CPUMGetHyperEBX(pVCpu)));
} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
uint64_t TickEnd = ASMReadTSC();
uint64_t tsEnd = RTTimeNanoTS();
uint64_t Elapsed = tsEnd - tsBegin;
uint64_t PerIteration = Elapsed / (uint64_t)i;
uint64_t cTicksElapsed = TickEnd - TickStart;
uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
/*
* These forced actions are not necessary for the test and trigger breakpoints too.
*/
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
/*
* Profile switching.
*/
RTPrintf("VMM: profiling switcher...\n");
Log(("VMM: profiling switcher...\n"));
uint64_t TickMin = ~0;
tsBegin = RTTimeNanoTS();
TickStart = ASMReadTSC();
Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
for (i = 0; i < 1000000; i++)
{
CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
CPUMPushHyper(pVCpu, 0);
CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_NOP);
CPUMPushHyper(pVCpu, pVM->pVMRC);
CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
uint64_t TickThisStart = ASMReadTSC();
rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
if (RT_LIKELY(rc == VINF_SUCCESS))
rc = pVCpu->vmm.s.iLastGZRc;
uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
if (RT_FAILURE(rc))
{
Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
VMMR3FatalDump(pVM, pVCpu, rc);
return rc;
}
if (TickThisElapsed < TickMin)
TickMin = TickThisElapsed;
}
TickEnd = ASMReadTSC();
tsEnd = RTTimeNanoTS();
Elapsed = tsEnd - tsBegin;
PerIteration = Elapsed / (uint64_t)i;
cTicksElapsed = TickEnd - TickStart;
cTicksPerIteration = cTicksElapsed / (uint64_t)i;
RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
rc = VINF_SUCCESS;
}
else
AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
#endif
return rc;
}