Esempio n. 1
0
SYS_MODULE_OBJ STIMULUS_USART_DRV_Initialize(const SYS_MODULE_INDEX index,
                                       const SYS_MODULE_INIT * const init )
{
    /* Get the USART COnfig Data */
    configData = (DRV_USART_CONFIG_INIT *)init;
    /* Initialize USART */
    PLIB_USART_BaudRateSet(configData->usartId, SYS_CLK_PeripheralFrequencyGet(CLK_BUS_PERIPHERAL_1), configData->baudRate);
    PLIB_USART_HandshakeModeSelect(configData->usartId, USART_HANDSHAKE_MODE_FLOW_CONTROL);
    PLIB_USART_OperationModeSelect(configData->usartId, USART_ENABLE_TX_RX_USED);
    PLIB_USART_LineControlModeSelect(configData->usartId, configData->lineControl);
    PLIB_USART_TransmitterEnable(configData->usartId);
    PLIB_USART_TransmitterInterruptModeSelect(configData->usartId, USART_TRANSMIT_FIFO_NOT_FULL);
    PLIB_USART_ReceiverEnable(configData->usartId);
    PLIB_USART_ReceiverInterruptModeSelect(configData->usartId, configData->rxIntMode);
    /* Initialize interrupts */
    /* Note: TX interrupt must be enabled when data is ready to be transmitted */
    /* The following code can be used to enable TX Interrupt */
    /* PLIB_INT_SourceEnable(INT_ID_0, INT_SOURCE_USART_1_TRANSMIT); */
    PLIB_INT_SourceEnable(INT_ID_0, INT_SOURCE_USART_1_RECEIVE);
    PLIB_INT_SourceEnable(INT_ID_0, INT_SOURCE_USART_1_ERROR);
    PLIB_INT_VectorPrioritySet(INT_ID_0, INT_VECTOR_UART1, INT_PRIORITY_LEVEL1);
    PLIB_INT_VectorSubPrioritySet(INT_ID_0, INT_VECTOR_UART1, INT_SUBPRIORITY_LEVEL0);
    
    PLIB_USART_Enable(configData->usartId);
}
Esempio n. 2
0
void DRV_USART0_Initialize(void)
{
    /* Initialize USART */
    PLIB_USART_BaudRateSet(USART_ID_1, SYS_CLK_PeripheralFrequencyGet(CLK_BUS_PERIPHERAL_2), 9600);
    PLIB_USART_HandshakeModeSelect(USART_ID_1, USART_HANDSHAKE_MODE_FLOW_CONTROL);
    PLIB_USART_OperationModeSelect(USART_ID_1, USART_ENABLE_TX_RX_USED);
    PLIB_USART_LineControlModeSelect(USART_ID_1, USART_8N1);
    PLIB_USART_TransmitterEnable(USART_ID_1);
    PLIB_USART_TransmitterInterruptModeSelect(USART_ID_1, USART_TRANSMIT_FIFO_NOT_FULL);
    PLIB_USART_ReceiverEnable(USART_ID_1);
    PLIB_USART_ReceiverInterruptModeSelect(USART_ID_1, USART_RECEIVE_FIFO_ONE_CHAR);

    /* Initialize TX interrupt */
    PLIB_INT_SourceEnable(INT_ID_0, INT_SOURCE_USART_1_TRANSMIT);
    PLIB_INT_VectorPrioritySet(INT_ID_0, INT_VECTOR_UART1_TX, INT_PRIORITY_LEVEL1);
    PLIB_INT_VectorSubPrioritySet(INT_ID_0, INT_VECTOR_UART1_TX, INT_SUBPRIORITY_LEVEL0);

    /* Initialize RX interrupt */
    PLIB_INT_SourceEnable(INT_ID_0, INT_SOURCE_USART_1_RECEIVE);
    PLIB_INT_VectorPrioritySet(INT_ID_0, INT_VECTOR_UART1_RX, INT_PRIORITY_LEVEL1);
    PLIB_INT_VectorSubPrioritySet(INT_ID_0, INT_VECTOR_UART1_RX, INT_SUBPRIORITY_LEVEL0);

    /* Initialize Fault interrupt */
    PLIB_INT_SourceEnable(INT_ID_0, INT_SOURCE_USART_1_ERROR);
    PLIB_INT_VectorPrioritySet(INT_ID_0, INT_VECTOR_UART1_FAULT, INT_PRIORITY_LEVEL1);
    PLIB_INT_VectorSubPrioritySet(INT_ID_0, INT_VECTOR_UART1_FAULT, INT_SUBPRIORITY_LEVEL0);

    PLIB_USART_Enable(USART_ID_1);
}
Esempio n. 3
0
void DRV_USART0_Initialize(void)
{
    /* Initialize USART */
    PLIB_USART_BaudRateSet(USART_ID_1, SYS_CLK_PeripheralFrequencyGet(CLK_BUS_PERIPHERAL_1), 115200);
    PLIB_USART_HandshakeModeSelect(USART_ID_1, USART_HANDSHAKE_MODE_SIMPLEX);
    PLIB_USART_OperationModeSelect(USART_ID_1, USART_ENABLE_TX_RX_USED);
    PLIB_USART_LineControlModeSelect(USART_ID_1, USART_8N1);
    PLIB_USART_TransmitterEnable(USART_ID_1);
    PLIB_USART_TransmitterInterruptModeSelect(USART_ID_1, USART_TRANSMIT_FIFO_EMPTY);

    PLIB_USART_Enable(USART_ID_1);
}
Esempio n. 4
0
void DRV_USART0_Initialize(void)
{
    /* Initialize USART */
    PLIB_USART_BaudRateSet(USART_ID_2, SYS_CLK_PeripheralFrequencyGet(CLK_BUS_PERIPHERAL_1), 230400);
    PLIB_USART_HandshakeModeSelect(USART_ID_2, USART_HANDSHAKE_MODE_SIMPLEX);
    PLIB_USART_OperationModeSelect(USART_ID_2, USART_ENABLE_TX_RX_USED);
    PLIB_USART_LineControlModeSelect(USART_ID_2, USART_8N1);
    PLIB_USART_TransmitterEnable(USART_ID_2);
    PLIB_USART_TransmitterInterruptModeSelect(USART_ID_2, USART_TRANSMIT_FIFO_NOT_FULL);
    /* Initialize interrupts */
    /* Note: TX interrupt must be enabled when data is ready to be transmitted */
    /* The following code can be used to enable TX Interrupt */
    /* PLIB_INT_SourceEnable(INT_ID_0, INT_SOURCE_USART_2_TRANSMIT); */
    PLIB_INT_SourceEnable(INT_ID_0, INT_SOURCE_USART_2_ERROR);
    PLIB_INT_VectorPrioritySet(INT_ID_0, INT_VECTOR_UART2, INT_PRIORITY_LEVEL1);
    PLIB_INT_VectorSubPrioritySet(INT_ID_0, INT_VECTOR_UART2, INT_SUBPRIORITY_LEVEL0);

    PLIB_USART_Enable(USART_ID_2);
}