DIV_TOPC1, 24, 4), DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", DIV_TOPC3, 0, 4), DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", DIV_TOPC3, 8, 4), DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", DIV_TOPC3, 12, 4), DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", DIV_TOPC3, 16, 4), DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", DIV_TOPC3, 28, 4), }; static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { PLL_36XX_RATE(491520000, 20, 1, 0, 31457), {}, }; static struct samsung_gate_clock topc_gate_clks[] __initdata = { GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", ENABLE_ACLK_TOPC0, 4, 0, 0), GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", ENABLE_ACLK_TOPC1, 20, 0, 0), GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66", ENABLE_ACLK_TOPC1, 24, 0, 0), GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", ENABLE_SCLK_TOPC1, 20, 0, 0),
GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub", GATE_IP_ISP0, 13, 0, 0), GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub", GATE_IP_ISP1, 4, 0, 0), GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub", GATE_IP_ISP1, 5, 0, 0), GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub", GATE_IP_ISP1, 6, 0, 0), GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub", GATE_IP_ISP1, 7, 0, 0), }; static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ PLL_36XX_RATE(266000000, 266, 3, 3, 0), /* Not in UM, but need for eDP on snow */ PLL_36XX_RATE(70500000, 94, 2, 4, 0), { }, }; static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ PLL_36XX_RATE(192000000, 64, 2, 2, 0), PLL_36XX_RATE(180633600, 90, 3, 2, 20762), PLL_36XX_RATE(180000000, 90, 3, 2, 0), PLL_36XX_RATE(73728000, 98, 2, 4, 19923), PLL_36XX_RATE(67737600, 90, 2, 4, 20762), PLL_36XX_RATE(49152000, 98, 3, 4, 19923), PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
PLL_35XX_RATE(1200000000, 200, 4, 0), PLL_35XX_RATE(1100000000, 275, 6, 0), PLL_35XX_RATE(1000000000, 125, 3, 0), PLL_35XX_RATE( 900000000, 150, 4, 0), PLL_35XX_RATE( 800000000, 100, 3, 0), PLL_35XX_RATE( 700000000, 175, 3, 1), PLL_35XX_RATE( 600000000, 200, 4, 1), PLL_35XX_RATE( 500000000, 125, 3, 1), PLL_35XX_RATE( 400000000, 100, 3, 1), PLL_35XX_RATE( 300000000, 200, 4, 2), PLL_35XX_RATE( 200000000, 100, 3, 2), { /* sentinel */ } }; static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { PLL_36XX_RATE(192000000, 48, 3, 1, 0), PLL_36XX_RATE(180633605, 45, 3, 1, 10381), PLL_36XX_RATE(180000000, 45, 3, 1, 0), PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), { /* sentinel */ } }; static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = { PLL_36XX_RATE(533000000, 133, 3, 1, 16384), PLL_36XX_RATE(440000000, 110, 3, 1, 0), PLL_36XX_RATE(350000000, 175, 3, 2, 0), PLL_36XX_RATE(266000000, 133, 3, 2, 0), PLL_36XX_RATE(160000000, 160, 3, 3, 0),
PLL_35XX_RATE(520000000, 260, 3, 2), PLL_35XX_RATE(500000000, 250, 3, 2), PLL_35XX_RATE(440000000, 220, 3, 2), PLL_35XX_RATE(400000000, 200, 3, 2), PLL_35XX_RATE(350000000, 175, 3, 2), PLL_35XX_RATE(300000000, 300, 3, 3), PLL_35XX_RATE(266000000, 266, 3, 3), PLL_35XX_RATE(200000000, 200, 3, 3), PLL_35XX_RATE(160000000, 160, 3, 3), PLL_35XX_RATE(100000000, 200, 3, 4), { /* sentinel */ } }; /* EPLL */ static struct samsung_pll_rate_table exynos4415_epll_rates[] = { PLL_36XX_RATE(800000000, 200, 3, 1, 0), PLL_36XX_RATE(288000000, 96, 2, 2, 0), PLL_36XX_RATE(192000000, 128, 2, 3, 0), PLL_36XX_RATE(144000000, 96, 2, 3, 0), PLL_36XX_RATE(96000000, 128, 2, 4, 0), PLL_36XX_RATE(84000000, 112, 2, 4, 0), PLL_36XX_RATE(80750011, 107, 2, 4, 43691), PLL_36XX_RATE(73728004, 98, 2, 4, 19923), PLL_36XX_RATE(67987602, 271, 3, 5, 62285), PLL_36XX_RATE(65911004, 175, 2, 5, 49982), PLL_36XX_RATE(50000000, 200, 3, 5, 0), PLL_36XX_RATE(49152003, 131, 2, 5, 4719), PLL_36XX_RATE(48000000, 128, 2, 5, 0), PLL_36XX_RATE(45250000, 181, 3, 5, 0), { /* sentinel */ } };
PLL_35XX_RATE( 800000000, 200, 3, 1), PLL_35XX_RATE( 700000000, 175, 3, 1), PLL_35XX_RATE( 667000000, 667, 12, 1), PLL_35XX_RATE( 600000000, 400, 4, 2), PLL_35XX_RATE( 533000000, 533, 6, 2), PLL_35XX_RATE( 520000000, 260, 3, 2), PLL_35XX_RATE( 500000000, 250, 3, 2), PLL_35XX_RATE( 400000000, 200, 3, 2), PLL_35XX_RATE( 200000000, 200, 3, 3), PLL_35XX_RATE( 100000000, 200, 3, 4), { /* sentinel */ } }; /* EPLL */ static struct samsung_pll_rate_table exynos3250_epll_rates[] = { PLL_36XX_RATE(800000000, 200, 3, 1, 0), PLL_36XX_RATE(288000000, 96, 2, 2, 0), PLL_36XX_RATE(192000000, 128, 2, 3, 0), PLL_36XX_RATE(144000000, 96, 2, 3, 0), PLL_36XX_RATE( 96000000, 128, 2, 4, 0), PLL_36XX_RATE( 84000000, 112, 2, 4, 0), PLL_36XX_RATE( 80000004, 106, 2, 4, 43691), PLL_36XX_RATE( 73728000, 98, 2, 4, 19923), PLL_36XX_RATE( 67737598, 270, 3, 5, 62285), PLL_36XX_RATE( 65535999, 174, 2, 5, 49982), PLL_36XX_RATE( 50000000, 200, 3, 5, 0), PLL_36XX_RATE( 49152002, 131, 2, 5, 4719), PLL_36XX_RATE( 48000000, 128, 2, 5, 0), PLL_36XX_RATE( 45158401, 180, 3, 5, 41524), { /* sentinel */ } };
PLL_35XX_RATE( 800000000, 200, 3, 1), PLL_35XX_RATE( 700000000, 175, 3, 1), PLL_35XX_RATE( 667000000, 667, 12, 1), PLL_35XX_RATE( 600000000, 400, 4, 2), PLL_35XX_RATE( 533000000, 533, 6, 2), PLL_35XX_RATE( 520000000, 260, 3, 2), PLL_35XX_RATE( 500000000, 250, 3, 2), PLL_35XX_RATE( 400000000, 200, 3, 2), PLL_35XX_RATE( 200000000, 200, 3, 3), PLL_35XX_RATE( 100000000, 200, 3, 4), { /* sentinel */ } }; /* VPLL */ static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { PLL_36XX_RATE(600000000, 100, 2, 1, 0), PLL_36XX_RATE(533000000, 266, 3, 2, 32768), PLL_36XX_RATE(519230987, 173, 2, 2, 5046), PLL_36XX_RATE(500000000, 250, 3, 2, 0), PLL_36XX_RATE(445500000, 148, 2, 2, 32768), PLL_36XX_RATE(445055007, 148, 2, 2, 23047), PLL_36XX_RATE(400000000, 200, 3, 2, 0), PLL_36XX_RATE(371250000, 123, 2, 2, 49152), PLL_36XX_RATE(370878997, 185, 3, 2, 28803), PLL_36XX_RATE(340000000, 170, 3, 2, 0), PLL_36XX_RATE(335000015, 111, 2, 2, 43691), PLL_36XX_RATE(333000000, 111, 2, 2, 0), PLL_36XX_RATE(330000000, 110, 2, 2, 0), PLL_36XX_RATE(320000015, 106, 2, 2, 43691), PLL_36XX_RATE(300000000, 100, 2, 2, 0), PLL_36XX_RATE(275000000, 275, 3, 3, 0),