static void
ppbattach(device_t parent, device_t self, void *aux)
{
struct ppb_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
struct pcibus_attach_args pba;
pcireg_t busdata;
pci_aprint_devinfo(pa, NULL);
sc->sc_pc = pc;
sc->sc_tag = pa->pa_tag;
sc->sc_dev = self;
busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
aprint_normal_dev(self, "not configured by system firmware\n");
return;
}
ppb_fix_pcie(self);
#if 0
/*
* XXX can't do this, because we're not given our bus number
* (we shouldn't need it), and because we've no way to
* decompose our tag.
*/
/* sanity check. */
if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
#endif
if (!pmf_device_register(self, ppb_suspend, ppb_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
/*
* Attach the PCI bus than hangs off of it.
*
* XXX Don't pass-through Memory Read Multiple. Should we?
* XXX Consult the spec...
*/
pba.pba_iot = pa->pa_iot;
pba.pba_memt = pa->pa_memt;
pba.pba_dmat = pa->pa_dmat;
pba.pba_dmat64 = pa->pa_dmat64;
pba.pba_pc = pc;
pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
pba.pba_sub = PPB_BUSINFO_SUBORDINATE(busdata);
pba.pba_bridgetag = &sc->sc_tag;
pba.pba_intrswiz = pa->pa_intrswiz;
pba.pba_intrtag = pa->pa_intrtag;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
static int
i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset,
struct pciconf_state *ps)
{
pcireg_t binfo;
int pbus, sbus;
if ((unsigned int)offset >= PCI_CONF_SIZE)
return (1);
i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
pbus = PPB_BUSINFO_PRIMARY(binfo);
sbus = PPB_BUSINFO_SECONDARY(binfo);
/*
* If the bus # is the Primary bus #, use the Primary
* Address/Data registers, otherwise use the Secondary
* Address/Data registers.
*/
if (ps->ps_b == pbus) {
ps->ps_addr_reg = I80312_ATU_POCCA;
ps->ps_data_reg = I80312_ATU_POCCD;
ps->ps_csr_reg = PCI_COMMAND_STATUS_REG;
} else {
ps->ps_addr_reg = I80312_ATU_SOCCA;
ps->ps_data_reg = I80312_ATU_SOCCD;
ps->ps_csr_reg = I80312_ATU_SACS;
}
/*
* If the bus # is the Primary or Secondary bus #, then use
* Type 0 cycles, else use Type 1.
*
* XXX We should filter out all non-private devices here!
* XXX How does private space interact with PCI-PCI bridges?
*/
if (ps->ps_b == pbus || ps->ps_b == sbus) {
if (ps->ps_d > (31 - 11))
return (1);
ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) |
offset;
} else {
/* The tag is already in the correct format. */
ps->ps_addr_val = tag | offset | 1;
}
return (0);
}
void
ppbattach(struct device *parent, struct device *self, void *aux)
{
struct ppb_softc *sc = (struct ppb_softc *)self;
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
struct pcibus_attach_args pba;
pci_intr_handle_t ih;
pcireg_t busdata, reg, blr;
char *name;
int pin;
sc->sc_pc = pc;
sc->sc_tag = pa->pa_tag;
busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
printf(": not configured by system firmware\n");
return;
}
#if 0
/*
* XXX can't do this, because we're not given our bus number
* (we shouldn't need it), and because we've no way to
* decompose our tag.
*/
/* sanity check. */
if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
#endif
/* Check for PCI Express capabilities and setup hotplug support. */
if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
&sc->sc_cap_off, ®) && (reg & PCI_PCIE_XCAP_SI)) {
#ifdef __i386__
if (pci_intr_map(pa, &ih) == 0)
sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO,
ppb_intr, sc, self->dv_xname);
#else
if (pci_intr_map_msi(pa, &ih) == 0 ||
pci_intr_map(pa, &ih) == 0)
sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO,
ppb_intr, sc, self->dv_xname);
#endif
if (sc->sc_intrhand) {
printf(": %s", pci_intr_string(pc, ih));
/* Enable hotplug interrupt. */
reg = pci_conf_read(pc, pa->pa_tag,
sc->sc_cap_off + PCI_PCIE_SLCSR);
reg |= (PCI_PCIE_SLCSR_HPE | PCI_PCIE_SLCSR_PDE);
pci_conf_write(pc, pa->pa_tag,
sc->sc_cap_off + PCI_PCIE_SLCSR, reg);
timeout_set(&sc->sc_to, ppb_hotplug_insert_finish, sc);
}
}
printf("\n");
if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL ||
(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82801BA_HPB &&
PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82801BAM_HPB))
ppb_alloc_resources(sc, pa);
for (pin = PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_D; pin++) {
pa->pa_intrpin = pa->pa_rawintrpin = pin;
pa->pa_intrline = 0;
pci_intr_map(pa, &sc->sc_ih[pin - PCI_INTERRUPT_PIN_A]);
}
/*
* The UltraSPARC-IIi APB doesn't implement the standard
* address range registers.
*/
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SIMBA)
goto attach;
/* Figure out the I/O address range of the bridge. */
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IOSTATUS);
sc->sc_iobase = (blr & 0x000000f0) << 8;
sc->sc_iolimit = (blr & 0x000f000) | 0x00000fff;
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IO_HI);
sc->sc_iobase |= (blr & 0x0000ffff) << 16;
sc->sc_iolimit |= (blr & 0xffff0000);
if (sc->sc_iolimit > sc->sc_iobase) {
name = malloc(32, M_DEVBUF, M_NOWAIT);
if (name) {
snprintf(name, 32, "%s pciio", sc->sc_dev.dv_xname);
sc->sc_ioex = extent_create(name, 0, 0xffffffff,
M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
extent_free(sc->sc_ioex, sc->sc_iobase,
sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT);
}
}
/* Figure out the memory mapped I/O address range of the bridge. */
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_MEM);
sc->sc_membase = (blr & 0x0000fff0) << 16;
sc->sc_memlimit = (blr & 0xfff00000) | 0x000fffff;
if (sc->sc_memlimit > sc->sc_membase) {
name = malloc(32, M_DEVBUF, M_NOWAIT);
if (name) {
snprintf(name, 32, "%s pcimem", sc->sc_dev.dv_xname);
sc->sc_memex = extent_create(name, 0, 0xffffffff,
M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
extent_free(sc->sc_memex, sc->sc_membase,
sc->sc_memlimit - sc->sc_membase + 1,
EX_NOWAIT);
}
}
/* Figure out the prefetchable MMI/O address range of the bridge. */
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFMEM);
sc->sc_pmembase = (blr & 0x0000fff0) << 16;
sc->sc_pmemlimit = (blr & 0xfff00000) | 0x000fffff;
#ifdef __LP64__ /* XXX because extents use long... */
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFBASE_HI32);
sc->sc_pmembase |= ((uint64_t)blr) << 32;
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFLIM_HI32);
sc->sc_pmemlimit |= ((uint64_t)blr) << 32;
#endif
if (sc->sc_pmemlimit > sc->sc_pmembase) {
name = malloc(32, M_DEVBUF, M_NOWAIT);
if (name) {
snprintf(name, 32, "%s pcipmem", sc->sc_dev.dv_xname);
sc->sc_pmemex = extent_create(name, 0, (u_long)-1L,
M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
extent_free(sc->sc_pmemex, sc->sc_pmembase,
sc->sc_pmemlimit - sc->sc_pmembase + 1,
EX_NOWAIT);
}
}
/*
* The Intel 82801BAM Hub-to-PCI can decode subtractively.
* XXX We probably should handle subtractive decode bridges
* in general.
*/
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BA_HPB ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_HPB)) {
if (sc->sc_ioex == NULL)
sc->sc_ioex = pa->pa_ioex;
if (sc->sc_memex == NULL)
sc->sc_memex = pa->pa_memex;
}
attach:
/*
* Attach the PCI bus that hangs off of it.
*
* XXX Don't pass-through Memory Read Multiple. Should we?
* XXX Consult the spec...
*/
bzero(&pba, sizeof(pba));
pba.pba_busname = "pci";
pba.pba_iot = pa->pa_iot;
pba.pba_memt = pa->pa_memt;
pba.pba_dmat = pa->pa_dmat;
pba.pba_pc = pc;
pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
pba.pba_ioex = sc->sc_ioex;
pba.pba_memex = sc->sc_memex;
pba.pba_pmemex = sc->sc_pmemex;
pba.pba_domain = pa->pa_domain;
pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
pba.pba_bridgeih = sc->sc_ih;
pba.pba_bridgetag = &sc->sc_tag;
pba.pba_intrswiz = pa->pa_intrswiz;
pba.pba_intrtag = pa->pa_intrtag;
sc->sc_psc = config_found(self, &pba, ppbprint);
}
void
pchbattach(struct device *parent, struct device *self, void *aux)
{
struct pchb_softc *sc = (struct pchb_softc *)self;
struct pci_attach_args *pa = aux;
struct pcibus_attach_args pba;
pcireg_t bcreg, bir;
u_char pbnum;
pcitag_t tag;
int i, r;
int doattach = 0;
switch (PCI_VENDOR(pa->pa_id)) {
case PCI_VENDOR_AMD:
printf("\n");
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_AMD_AMD64_0F_HT:
case PCI_PRODUCT_AMD_AMD64_10_HT:
for (i = 0; i < AMD64HT_NUM_LDT; i++)
pchb_amd64ht_attach(self, pa, i);
break;
}
break;
case PCI_VENDOR_INTEL:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_INTEL_82915G_HB:
case PCI_PRODUCT_INTEL_82945G_HB:
case PCI_PRODUCT_INTEL_82925X_HB:
case PCI_PRODUCT_INTEL_82955X_HB:
sc->sc_bt = pa->pa_memt;
if (bus_space_map(sc->sc_bt, I82802_IOBASE,
I82802_IOSIZE, 0, &sc->sc_bh))
break;
/* probe and init rng */
if (!(bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_HWST) & I82802_RNG_HWST_PRESENT))
break;
/* enable RNG */
bus_space_write_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_HWST,
bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_HWST) | I82802_RNG_HWST_ENABLE);
/* see if we can read anything */
for (i = 1000; i-- &&
!(bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_RNGST) & I82802_RNG_RNGST_DATAV); )
DELAY(10);
if (!(bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_RNGST) & I82802_RNG_RNGST_DATAV))
break;
r = bus_space_read_1(sc->sc_bt, sc->sc_bh,
I82802_RNG_DATA);
timeout_set(&sc->sc_rng_to, pchb_rnd, sc);
sc->sc_rng_i = 4;
pchb_rnd(sc);
sc->sc_rng_active = 1;
break;
}
printf("\n");
break;
case PCI_VENDOR_VIATECH:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_VIATECH_VT8251_PCIE_0:
/*
* Bump the host bridge into PCI-PCI bridge
* mode by clearing magic bit on the VLINK
* device. This allows us to read the bus
* number for the PCI bus attached to this
* host bridge.
*/
tag = pci_make_tag(pa->pa_pc, 0, 17, 7);
bcreg = pci_conf_read(pa->pa_pc, tag, 0xfc);
bcreg &= ~0x00000004; /* XXX Magic */
pci_conf_write(pa->pa_pc, tag, 0xfc, bcreg);
bir = pci_conf_read(pa->pa_pc,
pa->pa_tag, PPB_REG_BUSINFO);
pbnum = PPB_BUSINFO_PRIMARY(bir);
if (pbnum > 0)
doattach = 1;
/* Switch back to host bridge mode. */
bcreg |= 0x00000004; /* XXX Magic */
pci_conf_write(pa->pa_pc, tag, 0xfc, bcreg);
break;
}
printf("\n");
break;
default:
printf("\n");
break;
}
#if NAGP > 0
/*
* Intel IGD have an odd interface and attach at vga, however,
* in that mode they don't have the AGP cap bit, so this
* test should be sufficient
*/
if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
NULL, NULL) != 0) {
struct agp_attach_args aa;
aa.aa_busname = "agp";
aa.aa_pa = pa;
config_found(self, &aa, agpdev_print);
}
#endif /* NAGP > 0 */
if (doattach == 0)
return;
bzero(&pba, sizeof(pba));
pba.pba_busname = "pci";
pba.pba_iot = pa->pa_iot;
pba.pba_memt = pa->pa_memt;
pba.pba_dmat = pa->pa_dmat;
pba.pba_busex = pa->pa_busex;
pba.pba_domain = pa->pa_domain;
pba.pba_bus = pbnum;
pba.pba_pc = pa->pa_pc;
config_found(self, &pba, pchb_print);
}
/*
* The Npwr routes #INTA of the on-board PCI devices directly
* through the CPLD. There is no PCI-PCI bridge and no PCI
* slots on the Npwr.
*
* We also expect the devices to be on the Secondary side of
* the i80312.
*/
reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
sbus = PPB_BUSINFO_SECONDARY(reg);
if (pa->pa_bus != sbus) {
printf("iq80310_pci_intr_map: %d/%d/%d not on Secondary bus\n",
pa->pa_bus, pa->pa_device, pa->pa_function);
return (1);
}
switch (pa->pa_device) {
case 5: /* LSI 53c1010 SCSI */
*ihp = XINT3_IRQ(2);
break;
case 6: /* Intel i82544GC Gig-E #1 */
*ihp = XINT3_IRQ(1);
break;
case 7: /* Intel i82544GC Gig-E #2 */
*ihp = XINT3_IRQ(4);
break;
default:
printf("iq80310_pci_intr_map: no mapping for %d/%d/%d\n",
pa->pa_bus, pa->pa_device, pa->pa_function);
return (1);
}
return (0);
}
#else /* Default to stock IQ80310 */
int
iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
pcitag_t tag;
pcireg_t reg;
int sbus, pbus;
/*
* Mapping of PCI interrupts on the IQ80310 is pretty easy; there
* is a single interrupt line for all PCI devices on pre-F boards,
* and an interrupt line for each INTx# signal on F and later boards.
*
* The only exception is the on-board Ethernet; this devices has
* its own dedicated interrupt line. The location of this device
* looks like this:
*
* 80312 Secondary -> PPB at dev #7 -> i82559 at dev #0
*
* In order to determine if we're mapping the interrupt for the
* on-board Ethernet, we must read the Secondary Bus # of the
* i80312, then use that to read the Secondary Bus # of the
* 21154 PPB. At that point, we know that b/d/f of the i82559,
* and can determine if we're looking at that device.
*/
reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
pbus = PPB_BUSINFO_PRIMARY(reg);
sbus = PPB_BUSINFO_SECONDARY(reg);
/*
* XXX We don't know how to map interrupts on the Primary
* XXX PCI bus right now.
*/
if (pa->pa_bus == pbus) {
printf("iq80310_pci_intr_map: can't map interrupts on "
"Primary bus\n");
return (1);
}
tag = pci_make_tag(pa->pa_pc, sbus, 7, 0);
/* Make sure the PPB is there. */
reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
PCI_VENDOR(reg) == 0) {
/*
* That's odd... no PPB there? Oh well, issue a warning
* and continue on.
*/
printf("iq80310_pci_intr_map: PPB not found at %d/%d/%d ??\n",
sbus, 7, 0);
goto pinmap;
}
/* Make sure the device that's there is a PPB. */
reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) {
/*
* That's odd... the device that's there isn't a PPB.
* Oh well, issue a warning and continue on.
*/
printf("iq80310_pci_intr_map: %d/%d/%d isn't a PPB ??\n",
sbus, 7, 0);
goto pinmap;
}
/* Now read the PPB's secondary bus number. */
reg = pci_conf_read(pa->pa_pc, tag, PPB_REG_BUSINFO);
sbus = PPB_BUSINFO_SECONDARY(reg);
if (pa->pa_bus == sbus && pa->pa_device == 0 &&
pa->pa_function == 0) {
/* On-board i82559 Ethernet! */
*ihp = XINT3_IRQ(XINT3_ETHERNET);
return (0);
}
pinmap:
if (pa->pa_intrpin == 0) {
/* No IRQ used. */
return (1);
}
if (pa->pa_intrpin > 4) {
printf("iq80310_pci_intr_map: bad interrupt pin %d\n",
pa->pa_intrpin);
return (1);
}
/* INTD# is always in XINT3. */
if (pa->pa_intrpin == 4) {
*ihp = XINT3_IRQ(XINT3_SINTD);
return (0);
}
/* On pre-F boards, ALL of them are on XINT3. */
if (/*pre-F*/0)
*ihp = XINT3_IRQ(XINT3_SINTD);
else
*ihp = XINT0_IRQ(pa->pa_intrpin - 1);
return (0);
}
