static VOID
TSP_PowerOn(VOID)
{
TSPMSG((_T("[TSP] ++TSP_PowerOn()\r\n")));
g_pADCReg->ADCDLY = ADC_DELAY(TSP_ADC_DELAY);
g_pADCReg->ADCCON = RESSEL_12BIT | PRESCALER_EN | PRESCALER_VAL(TSP_ADC_PRESCALER) | STDBM_NORMAL;
g_pADCReg->ADCTSC = ADCTSC_WAIT_PENDOWN;
g_pADCReg->ADCCLRINT = CLEAR_ADC_INT;
g_pADCReg->ADCCLRWK = CLEAR_ADCWK_INT;
g_SampleTick_Low = TSP_TIMER_CNT_LOW;
g_SampleTick_High = TSP_TIMER_CNT_HIGH;
// Set Divider MUX for Timer3
SET_TIMER3_DIVIDER_MUX(g_pPWMReg, TSP_TIMER_DIVIDER);
g_pPWMReg->TCNTB3 = g_SampleTick_Low;
// timer3 interrupt disable
g_pPWMReg->TINT_CSTAT = TINT_CSTAT_INTMASK(g_pPWMReg->TINT_CSTAT) & ~TIMER3_INTERRUPT_ENABLE;
// timer3 interrupt status clear
g_pPWMReg->TINT_CSTAT = TINT_CSTAT_INTMASK(g_pPWMReg->TINT_CSTAT) | TIMER3_PENDING_CLEAR;
TSPMSG((_T("[TSP] --TSP_PowerOn()\r\n")));
}
static VOID
TSP_PowerOn(VOID)
{
TSPMSG((_T("[TSP] ++TSP_PowerOn()\r\n")));
g_pADCReg->ADCDLY = ADC_DELAY(TSP_ADC_DELAY);
g_pADCReg->ADCCON = PRESCALER_EN | PRESCALER_VAL(TSP_ADC_PRESCALER);
g_pADCReg->ADCTSC = ADCTSC_WAIT_PENDOWN;
g_pADCReg->ADCCLRINT = CLEAR_ADC_INT;
g_pADCReg->ADCCLRWK = CLEAR_ADCWK_INT;
g_SampleTick_Low = TSP_TIMER_CNT_LOW;
g_SampleTick_High = TSP_TIMER_CNT_HIGH;
// Set Divider MUX for Timer3
switch(TSP_TIMER_DIVIDER)
{
case 1:
g_pPWMReg->TCFG1 = (g_pPWMReg->TCFG1 & ~(0xf<<12)) | (0<<12);
break;
case 2:
g_pPWMReg->TCFG1 = (g_pPWMReg->TCFG1 & ~(0xf<<12)) | (1<<12);
break;
case 4:
g_pPWMReg->TCFG1 = (g_pPWMReg->TCFG1 & ~(0xf<<12)) | (2<<12);
break;
case 8:
g_pPWMReg->TCFG1 = (g_pPWMReg->TCFG1 & ~(0xf<<12)) | (3<<12);
break;
case 16:
g_pPWMReg->TCFG1 = (g_pPWMReg->TCFG1 & ~(0xf<<12)) | (4<<12);
break;
default:
g_pPWMReg->TCFG1 = (g_pPWMReg->TCFG1 & ~(0xf<<12)) | (0<<12);
break;
}
g_pPWMReg->TCNTB3 = g_SampleTick_Low;
// timer3 interrupt disable
//g_pPWMReg->TINT_CSTAT &= ~(1<<3); // Do not use OR/AND operation on TINTC_CSTAT
g_pPWMReg->TINT_CSTAT = TINT_CSTAT_INTMASK(g_pPWMReg->TINT_CSTAT) & ~TIMER3_INTERRUPT_ENABLE;
// timer3 interrupt status clear
//g_pPWMReg->TINT_CSTAT |= (1<<8); // Do not use OR/AND operation on TINTC_CSTAT
g_pPWMReg->TINT_CSTAT = TINT_CSTAT_INTMASK(g_pPWMReg->TINT_CSTAT) | TIMER3_PENDING_CLEAR;
TSPMSG((_T("[TSP] --TSP_PowerOn()\r\n")));
}
static int __devinit atmel_tsadcc_probe(struct platform_device *pdev)
{
struct atmel_tsadcc *ts_dev;
struct input_dev *input_dev;
struct resource *res;
struct at91_tsadcc_data *pdata = pdev->dev.platform_data;
int err = 0;
unsigned int prsc;
unsigned int reg;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "no mmio resource defined.\n");
return -ENXIO;
}
/* Allocate memory for device */
ts_dev = kzalloc(sizeof(struct atmel_tsadcc), GFP_KERNEL);
if (!ts_dev) {
dev_err(&pdev->dev, "failed to allocate memory.\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, ts_dev);
input_dev = input_allocate_device();
if (!input_dev) {
dev_err(&pdev->dev, "failed to allocate input device.\n");
err = -EBUSY;
goto err_free_mem;
}
ts_dev->irq = platform_get_irq(pdev, 0);
if (ts_dev->irq < 0) {
dev_err(&pdev->dev, "no irq ID is designated.\n");
err = -ENODEV;
goto err_free_dev;
}
if (!request_mem_region(res->start, resource_size(res),
"atmel tsadcc regs")) {
dev_err(&pdev->dev, "resources is unavailable.\n");
err = -EBUSY;
goto err_free_dev;
}
tsc_base = ioremap(res->start, resource_size(res));
if (!tsc_base) {
dev_err(&pdev->dev, "failed to map registers.\n");
err = -ENOMEM;
goto err_release_mem;
}
err = request_irq(ts_dev->irq, atmel_tsadcc_interrupt, IRQF_DISABLED,
pdev->dev.driver->name, ts_dev);
if (err) {
dev_err(&pdev->dev, "failed to allocate irq.\n");
goto err_unmap_regs;
}
ts_dev->clk = clk_get(&pdev->dev, "tsc_clk");
if (IS_ERR(ts_dev->clk)) {
dev_err(&pdev->dev, "failed to get ts_clk\n");
err = PTR_ERR(ts_dev->clk);
goto err_free_irq;
}
ts_dev->input = input_dev;
ts_dev->bufferedmeasure = 0;
snprintf(ts_dev->phys, sizeof(ts_dev->phys),
"%s/input0", dev_name(&pdev->dev));
input_dev->name = "atmel touch screen controller";
input_dev->phys = ts_dev->phys;
input_dev->dev.parent = &pdev->dev;
__set_bit(EV_ABS, input_dev->evbit);
input_set_abs_params(input_dev, ABS_X, 0, 0x3FF, 0, 0);
input_set_abs_params(input_dev, ABS_Y, 0, 0x3FF, 0, 0);
input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
/* clk_enable() always returns 0, no need to check it */
clk_enable(ts_dev->clk);
prsc = clk_get_rate(ts_dev->clk);
dev_info(&pdev->dev, "Master clock is set at: %d Hz\n", prsc);
if (!pdata)
goto err_fail;
if (!pdata->adc_clock)
pdata->adc_clock = ADC_DEFAULT_CLOCK;
prsc = (prsc / (2 * pdata->adc_clock)) - 1;
/* saturate if this value is too high */
if (cpu_is_at91sam9rl()) {
if (prsc > PRESCALER_VAL(ATMEL_TSADCC_PRESCAL))
prsc = PRESCALER_VAL(ATMEL_TSADCC_PRESCAL);
} else {
if (prsc > PRESCALER_VAL(ATMEL_TSADCC_EPRESCAL))
prsc = PRESCALER_VAL(ATMEL_TSADCC_EPRESCAL);
}
dev_info(&pdev->dev, "Prescaler is set at: %d\n", prsc);
reg = ATMEL_TSADCC_TSAMOD_TS_ONLY_MODE |
((0x00 << 5) & ATMEL_TSADCC_SLEEP) | /* Normal Mode */
((0x01 << 6) & ATMEL_TSADCC_PENDET) | /* Enable Pen Detect */
(prsc << 8) |
((0x26 << 16) & ATMEL_TSADCC_STARTUP) |
((pdata->pendet_debounce << 28) & ATMEL_TSADCC_PENDBC);
atmel_tsadcc_write(ATMEL_TSADCC_CR, ATMEL_TSADCC_SWRST);
atmel_tsadcc_write(ATMEL_TSADCC_MR, reg);
atmel_tsadcc_write(ATMEL_TSADCC_TRGR, ATMEL_TSADCC_TRGMOD_NONE);
atmel_tsadcc_write(ATMEL_TSADCC_TSR,
(pdata->ts_sample_hold_time << 24) & ATMEL_TSADCC_TSSHTIM);
atmel_tsadcc_read(ATMEL_TSADCC_SR);
atmel_tsadcc_write(ATMEL_TSADCC_IER, ATMEL_TSADCC_PENCNT);
/* All went ok, so register to the input system */
err = input_register_device(input_dev);
if (err)
goto err_fail;
return 0;
err_fail:
clk_disable(ts_dev->clk);
clk_put(ts_dev->clk);
err_free_irq:
free_irq(ts_dev->irq, ts_dev);
err_unmap_regs:
iounmap(tsc_base);
err_release_mem:
release_mem_region(res->start, resource_size(res));
err_free_dev:
input_free_device(input_dev);
err_free_mem:
kfree(ts_dev);
return err;
}
