VOID
PciePwrAutoPowerDownElectricalIdleDetector (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 Pif;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n");
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
PcieRegisterWriteField (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
0x0,
TRUE,
Pcie
);
PcieRegisterWriteField (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET,
D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH,
0x2,
TRUE,
Pcie
);
PcieRegisterWriteField (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
0x1,
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n");
}
AGESA_STATUS
PcieTopologySetCoreConfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
UINT64 ConfigurationSignature;
UINT8 NewConfigurationValue;
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
if (Status == AGESA_SUCCESS) {
IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n",
PcieFmDebugGetWrapperNameString (Wrapper),
CoreId,
PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue)
);
PcieRegisterWriteField (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET,
D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH,
NewConfigurationValue,
FALSE,
Pcie
);
} else {
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
PcieFmDebugGetWrapperNameString (Wrapper),
((UINT32*)&ConfigurationSignature)[1],
((UINT32*)&ConfigurationSignature)[0]
);
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
}
}
}
return Status;
}
/**
* PCie EP not present
*
*
* @param[in] CurrentEngine Pointer to engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieTrainingNotPresent (
IN PCIe_ENGINE_CONFIG *CurrentEngine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) {
} else {
PcieRegisterWriteField (
PcieConfigGetParentWrapper (CurrentEngine),
WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
1,
FALSE,
Pcie
);
}
PcieTrainingSetPortStateV2 (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
/**
* Prepare for reconfiguration
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyPrepareForReconfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
UINT8 CoreId;
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
0xf,
FALSE,
Pcie
);
}
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0;
D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
}
}
VOID
PcieAcsCapabilityWrapperEnableV4 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAcsCapabilityWrapperEnableV4 Enter\n");
if (!PcieLibIsPcieWrapper (Wrapper)) {
return;
}
//Step 1, Enable the ACS capability strap, which add ACS capability pointer to the PCIE extend capability list
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_00B0_ADDRESS),
D0F0xE4_CORE_00B0_Bitfield_6_6_OFFSET,
D0F0xE4_CORE_00B0_Bitfield_6_6_WIDTH,
0x1,
TRUE,
Pcie
);
}
//Step 2, Enable ACS capabilities strap, including sub-items, in WRP
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0000_ADDRESS),
D0F0xE4_WRAP_0000_Bitfield_24_24_MASK | D0F0xE4_WRAP_0000_Bitfield_25_25_MASK | D0F0xE4_WRAP_0000_Bitfield_26_26_MASK,
(0x1 << D0F0xE4_WRAP_0000_Bitfield_24_24_OFFSET) | (0x1 << D0F0xE4_WRAP_0000_Bitfield_25_25_OFFSET) | (0x1 << D0F0xE4_WRAP_0000_Bitfield_26_26_OFFSET),
TRUE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAcsCapabilityWrapperEnableV4 Exit\n");
}
VOID
PcieLockRegisters (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
0x1,
TRUE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n");
}
/**
* Release training
*
*
* @param[in] CurrentEngine Pointer to engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieTrainingRelease (
IN PCIe_ENGINE_CONFIG *CurrentEngine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 LinkTrainingState;
PcieRegisterWriteField (
PcieConfigGetParentWrapper (CurrentEngine),
WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
0,
FALSE,
Pcie
);
if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
LinkTrainingState = LinkStateCompliance;
} else {
LinkTrainingState = LinkStateDetectPresence;
}
PcieTrainingSetPortStateV2 (CurrentEngine, LinkTrainingState, TRUE, Pcie);
}
/**
* Set current link speed
*
*
* @param[in] LinkSpeedCapability Link Speed Capability
* @param[in] Engine Pointer to engine configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
PcieSetLinkSpeedCapV4 (
IN PCIE_LINK_SPEED_CAP LinkSpeedCapability,
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxF0xE4_xA4_STRUCT DxF0xE4_xA4;
DxF0xE4_xC0_STRUCT DxF0xE4_xC0;
DxF0x88_STRUCT DxF0x88;
GnbLibPciRead (
Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
AccessWidth32,
&DxF0x88.Value,
GnbLibGetHeader (Pcie)
);
DxF0xE4_xA4.Value = PciePortRegisterRead (
Engine,
DxF0xE4_xA4_ADDRESS,
Pcie
);
DxF0xE4_xC0.Value = PciePortRegisterRead (
Engine,
DxF0xE4_xC0_ADDRESS,
Pcie
);
switch (LinkSpeedCapability) {
case PcieGen3:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
DxF0xE4_xA4.Field.LcGen3EnStrap = 0x1;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
DxF0x88.Field.TargetLinkSpeed = 0x3;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
PciePortRegisterRMW (
Engine,
DxF0xE4_xA2_ADDRESS,
DxF0xE4_xA2_LcDynLanesPwrState_MASK,
(2 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET),
FALSE,
Pcie
);
break;
case PcieGen2:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
DxF0x88.Field.TargetLinkSpeed = 0x2;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
break;
case PcieGen1:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0;
DxF0x88.Field.TargetLinkSpeed = 0x1;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x1;
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId),
D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET,
D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH,
0,
FALSE,
Pcie
);
break;
default:
ASSERT (FALSE);
break;
}
if ((Pcie->PsppPolicy == PsppDisabled) || (PcieConfigIsSbPcieEngine (Engine))) {
DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0;
} else {
DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1;
}
PciePortRegisterWrite (
Engine,
DxF0xE4_xA4_ADDRESS,
DxF0xE4_xA4.Value,
FALSE,
Pcie
);
PciePortRegisterWrite (
Engine,
DxF0xE4_xC0_ADDRESS,
DxF0xE4_xC0.Value,
FALSE,
Pcie
);
GnbLibPciWrite (
Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
AccessWidth32,
&DxF0x88.Value,
GnbLibGetHeader (Pcie)
);
}
VOID
STATIC
PcieHwInitPowerGatingCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 Pif;
UINT32 Value;
D0F0xE4_PIF_0004_STRUCT D0F0xE4_PIF_0004;
D0F0xE4_PIF_0008_STRUCT D0F0xE4_PIF_0008;
D0F0xE4_PIF_000A_STRUCT D0F0xE4_PIF_000A;
D0F0xE4_CORE_012A_STRUCT D0F0xE4_CORE_012A;
D0F0xE4_CORE_012C_STRUCT D0F0xE4_CORE_012C;
D0F0xE4_CORE_012D_STRUCT D0F0xE4_CORE_012D;
GNB_BUILD_OPTIONS_CZ *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Enter\n");
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, GnbLibGetHeader (Pcie));
ASSERT (GnbBuildOptionData != NULL);
Value = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) {
Value = 0x1;
}
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_003D_ADDRESS),
D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_OFFSET,
D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_WIDTH,
Value,
TRUE,
Pcie
);
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
D0F0xE4_PIF_0008.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
Pcie
);
D0F0xE4_PIF_000A.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
Pcie
);
D0F0xE4_PIF_0008.Field.TxpwrInOff = GnbBuildOptionData->CfgPcieTxpwrInOff;
D0F0xE4_PIF_000A.Field.RxpwrInOff = GnbBuildOptionData->CfgPcieRxpwrInOff;
D0F0xE4_PIF_000A.Field.RxEiDetInPs2Degrade = 0x0;
D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x0;
D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) {
D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x1;
D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x1;
}
D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x0;
D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingOffPg) == PcieHwInitPwrGatingOffPg) {
D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x1;
D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x1;
}
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A.Value,
TRUE,
Pcie
);
D0F0xE4_PIF_0004.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS),
Pcie
);
D0F0xE4_PIF_0004.Field.PifDegradePwrPllMode = 0x0;
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS),
D0F0xE4_PIF_0004.Value,
TRUE,
Pcie
);
}
D0F0xE4_CORE_012A.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS),
Pcie
);
D0F0xE4_CORE_012C.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS),
Pcie
);
D0F0xE4_CORE_012D.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS),
Pcie
);
D0F0xE4_CORE_012A.Field.LMLaneDegrade0 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade1 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade2 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade3 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused0 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused1 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused2 = 1;
D0F0xE4_CORE_012D.Field.LMLaneUnused3 = 1;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS),
D0F0xE4_CORE_012A.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS),
D0F0xE4_CORE_012C.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS),
D0F0xE4_CORE_012D.Value,
TRUE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Exit\n");
}
VOID
STATIC
PcieEarlyPortInitCallbackCZ (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Enter\n");
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
PciePortProgramRegisterTable (PortInitEarlyTableCZ.Table, PortInitEarlyTableCZ.Length, Engine, FALSE, Pcie);
IDS_OPTION_HOOK (IDS_GNB_EQUAL_PRESET, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
PcieSetLinkWidthCap (Engine, Pcie);
PcieCompletionTimeout (Engine, Pcie);
PcieLinkSetSlotCap (Engine, Pcie);
PcieLinkInitHotplugCZ (Engine, Pcie);
//Move EXTENDED_FMT_SUPPORTED stting from Mid to here.
PciePortRegisterRMW (
Engine,
DxFxxE4_xC1_ADDRESS,
DxFxxE4_xC1_StrapE2EPrefixEn_MASK | DxFxxE4_xC1_StrapExtendedFmtSupported_MASK,
(1 << DxFxxE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxFxxE4_xC1_StrapExtendedFmtSupported_OFFSET),
FALSE,
Pcie
);
if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
(Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
ASSERT (!PcieConfigIsSbPcieEngine (Engine));
//
// Pass endpoint status in scratch
//
PciePortRegisterRMW (
Engine,
DxFxxE4_x01_ADDRESS,
0x1,
0x1,
FALSE,
Pcie
);
PcieTrainingSetPortStateV2 (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
if (PcieConfigIsSbPcieEngine (Engine)) {
PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingSuccess, FALSE, Pcie);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_001C_ADDRESS),
D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_OFFSET,
D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
IDS_OPTION_HOOK (IDS_GNB_GEN1_LOOPBACK, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Exit\n");
}
VOID
STATIC
PcieLinkInitHotplugCZ (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxFxxE4_xB5_STRUCT DxFxxE4_xB5;
UINT32 Value;
if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
DxFxxE4_xB5.Value = PciePortRegisterRead (Engine, DxFxxE4_xB5_ADDRESS, Pcie);
DxFxxE4_xB5.Field.LcEhpRxPhyCmd = 0x3;
DxFxxE4_xB5.Field.LcEhpTxPhyCmd = 0x3;
DxFxxE4_xB5.Field.LcEnhancedHotPlugEn = 0x1;
DxFxxE4_xB5.Field.LcRcvrDetEnOverride = 0;
PciePortRegisterWrite (
Engine,
DxFxxE4_xB5_ADDRESS,
DxFxxE4_xB5.Value,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
0x5,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0118_ADDRESS),
D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_OFFSET,
D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
GnbLibPciRMW (
Engine->Type.Port.Address.AddressValue | DxFxx6C_ADDRESS,
AccessS3SaveWidth32,
0xffffffff,
1 << DxFxx6C_HotplugCapable_OFFSET,
GnbLibGetHeader (Pcie)
);
PciePortRegisterWriteField (
Engine,
DxFxxE4_x20_ADDRESS,
DxFxxE4_x20_TxFlushTlpDis_OFFSET,
DxFxxE4_x20_TxFlushTlpDis_WIDTH,
0x0,
TRUE,
Pcie
);
PciePortRegisterWriteField (
Engine,
DxFxxE4_x70_ADDRESS,
DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET,
DxFxxE4_x70_RxRcbCplTimeoutMode_WIDTH,
0x1,
FALSE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) {
Value = 1;
} else {
Value = 0;
}
PciePortRegisterWriteField (
Engine,
DxFxxE4_x10_ADDRESS,
DxFxxE4_x10_NativePmeEn_OFFSET,
DxFxxE4_x10_NativePmeEn_WIDTH,
Value,
TRUE,
Pcie
);
}
VOID
PciePwrClockGating (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011;
D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012;
D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014;
D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015;
D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n");
D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8011.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
Pcie
);
if (Wrapper->Features.ClkGating == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f;
D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f;
D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1;
}
if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
D0F0xE4_WRAP_8014.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
D0F0xE4_WRAP_8015.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
D0F0xE4_WRAP_8012.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011.Value,
TRUE,
Pcie
);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
0xf,
TRUE,
Pcie
);
}
if (Wrapper->Features.LclkGating == 0x1) {
D0F0xE4_WRAP_8016.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
D0F0xE4_WRAP_8016.Value,
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
}
VOID
PcieLinkInitHotplug (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxF0xE4_xB5_STRUCT DxF0xE4_xB5;
if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie);
DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3;
DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3;
DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1;
PciePortRegisterWrite (
Engine,
DxF0xE4_xB5_ADDRESS,
DxF0xE4_xB5.Value,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
0x5,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET,
D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
GnbLibPciRMW (
Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
AccessS3SaveWidth32,
0xffffffff,
1 << DxF0x6C_HotplugCapable_OFFSET,
GnbLibGetHeader (Pcie)
);
PciePortRegisterWriteField (
Engine,
DxF0xE4_x20_ADDRESS,
DxF0xE4_x20_TxFlushTlpDis_OFFSET,
DxF0xE4_x20_TxFlushTlpDis_WIDTH,
0x0,
TRUE,
Pcie
);
PciePortRegisterWriteField (
Engine,
DxF0xE4_x70_ADDRESS,
DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET,
DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH,
0x1,
FALSE,
Pcie
);
}
}
