void
Permedia3Restore(ScrnInfoPtr pScrn, GLINTRegPtr pReg)
{
GLINTPtr pGlint = GLINTPTR(pScrn);
CARD32 temp;
int i;
/* We can't rely on the vgahw layer copying the font information
* back properly, due to problems with MMIO access to VGA space
* so we memcpy the information using the slow routines */
if (pGlint->STATE)
xf86SlowBcopy((CARD8*)pGlint->VGAdata, (CARD8*)pGlint->FbBase, 65536);
if ((pGlint->numMultiDevices == 2) || (IS_J2000)) {
RESTOREREG(GCSRAperture);
}
if (pGlint->MultiAperture) {
RESTOREREG(GMultGLINTAperture);
RESTOREREG(GMultGLINT1);
RESTOREREG(GMultGLINT2);
}
/* Permedia 3 memory Timings */
RESTOREREG(PM3MemBypassWriteMask);
RESTOREREG(PM3ByAperture1Mode);
RESTOREREG(PM3ByAperture2Mode);
RESTOREREG(ChipConfig);
RESTOREREG(Aperture0);
RESTOREREG(Aperture1);
RESTOREREG(PM3FifoControl);
if (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_GAMMA)
RESTOREREG(DFIFODis);
RESTOREREG(FIFODis);
RESTOREREG(PMVideoControl);
RESTOREREG(PMHbEnd);
RESTOREREG(PMHgEnd);
RESTOREREG(PMScreenBase);
RESTOREREG(VClkCtl);
RESTOREREG(PMScreenStride);
RESTOREREG(PMHTotal);
RESTOREREG(PMHsStart);
RESTOREREG(PMHsEnd);
RESTOREREG(PMVTotal);
RESTOREREG(PMVbEnd);
RESTOREREG(PMVsStart);
RESTOREREG(PMVsEnd);
if (pGlint->UseFlatPanel) {
RESTOREREG(VSConfiguration);
RESTOREREG(VSBBase);
}
RESTOREREG(PM2VDACRDIndexControl);
P2VOUT(PM2VDACRDOverlayKey);
P2VOUT(PM2VDACRDSyncControl);
P2VOUT(PM2VDACRDMiscControl);
P2VOUT(PM2VDACRDDACControl);
P2VOUT(PM2VDACRDPixelSize);
P2VOUT(PM2VDACRDColorFormat);
for (i=0;i<768;i++) {
Permedia2WriteAddress(pScrn, i);
Permedia2WriteData(pScrn, pReg->cmap[i]);
}
temp = Permedia2vInIndReg(pScrn, PM2VDACIndexClockControl) & 0xFC;
P2VOUT(PM2VDACRDDClk0PreScale);
P2VOUT(PM2VDACRDDClk0FeedbackScale);
P2VOUT(PM2VDACRDDClk0PostScale);
Permedia2vOutIndReg(pScrn, PM2VDACIndexClockControl, 0x00, temp|0x03);
}
static void setregs(const unsigned char regs[], int mode)
{
int i;
unsigned int *p = (unsigned int *)(regs+VGA_TOTAL_REGS);
const unsigned char *q = regs+188;
unlock();
GLINT_SLOW_WRITE_REG(0xFF, PM2DACReadMask);
if(chiptype == cPM2V)
GLINT_SLOW_WRITE_REG(p[19], ChipConfig);
GLINT_SLOW_WRITE_REG(p[0], Aperture0);
GLINT_SLOW_WRITE_REG(p[1], Aperture1);
GLINT_SLOW_WRITE_REG(p[2], PMFramebufferWriteMask);
GLINT_SLOW_WRITE_REG(p[3], PMBypassWriteMask);
GLINT_SLOW_WRITE_REG(p[4], DFIFODis);
GLINT_SLOW_WRITE_REG(p[5], FIFODis);
if(0)
GLINT_SLOW_WRITE_REG(p[6], PMMemConfig);
GLINT_SLOW_WRITE_REG(p[17], PMVideoControl);
GLINT_SLOW_WRITE_REG(p[9], PMHgEnd);
GLINT_SLOW_WRITE_REG(p[16], PMScreenBase);
GLINT_SLOW_WRITE_REG(p[18], VClkCtl);
GLINT_SLOW_WRITE_REG(p[10], PMScreenStride);
GLINT_SLOW_WRITE_REG(p[7], PMHTotal);
GLINT_SLOW_WRITE_REG(p[8], PMHbEnd);
GLINT_SLOW_WRITE_REG(p[24], PMHsStart);
GLINT_SLOW_WRITE_REG(p[11], PMHsEnd);
GLINT_SLOW_WRITE_REG(p[12], PMVTotal);
GLINT_SLOW_WRITE_REG(p[13], PMVbEnd);
GLINT_SLOW_WRITE_REG(p[14], PMVsStart);
GLINT_SLOW_WRITE_REG(p[15], PMVsEnd);
if(chiptype != cPM2V)
GLINT_SLOW_WRITE_REG(p[19], ChipConfig);
for (i=0;i<768;i++) {
Permedia2WriteAddress(i);
Permedia2WriteData(regs[VGA_TOTAL_REGS + 128 + i]);
}
switch(chiptype) {
case cPM2:
Permedia2OutIndReg(PM2DACIndexMCR, 0x00, p[25]);
Permedia2OutIndReg(PM2DACIndexMDCR, 0x00, p[26]);
Permedia2OutIndReg(PM2DACIndexCMR, 0x00, p[27]);
Permedia2OutIndReg(PM2DACIndexClockAM, 0x00, p[20]);
Permedia2OutIndReg(PM2DACIndexClockAN, 0x00, p[21]);
Permedia2OutIndReg(PM2DACIndexClockAP, 0x00, p[22]);
break;
case cPM2V:
GLINT_SLOW_WRITE_REG(p[23],PM2VDACRDIndexControl);
Permedia2vOutIndReg(PM2VDACRDOverlayKey, 0x00, p[25]);
Permedia2vOutIndReg(PM2VDACRDSyncControl, 0x00, p[26]);
Permedia2vOutIndReg(PM2VDACRDMiscControl, 0x00, p[27]);
Permedia2vOutIndReg(PM2VDACRDDACControl, 0x00, p[28]);
Permedia2vOutIndReg(PM2VDACRDPixelSize, 0x00, p[29]);
Permedia2vOutIndReg(PM2VDACRDColorFormat, 0x00, p[30]);
i = Permedia2vInIndReg(PM2VDACIndexClockControl) & 0xFC;
Permedia2vOutIndReg(PM2VDACRDDClk0PreScale, 0x00, p[20]);
Permedia2vOutIndReg(PM2VDACRDDClk0FeedbackScale, 0x00, p[21]);
Permedia2vOutIndReg(PM2VDACRDDClk0PostScale, 0x00, p[22]);
Permedia2vOutIndReg(PM2VDACIndexClockControl, 0x00, i | 0x03);
for(i=0;i<6;i++)
Permedia2vOutIndReg(PM2VDACRDCursorPalette+i, 0x00, q[i]);
Permedia2vOutIndReg(PM2VDACRDCursorHotSpotX, 0x00, q[6]);
Permedia2vOutIndReg(PM2VDACRDCursorHotSpotY, 0x00, q[7]);
Permedia2vOutIndReg(PM2VDACRDCursorXLow, 0x00, q[8]);
Permedia2vOutIndReg(PM2VDACRDCursorXHigh, 0x00, q[9]);
Permedia2vOutIndReg(PM2VDACRDCursorYLow, 0x00, q[10]);
Permedia2vOutIndReg(PM2VDACRDCursorYHigh, 0x00, q[11]);
Permedia2vOutIndReg(PM2DACCursorControl, 0x00, q[12]);
Permedia2vOutIndReg(PM2VDACRDCursorMode, 0x00, q[13]);
}
}
void
Permedia3PreInit(ScrnInfoPtr pScrn)
{
GLINTPtr pGlint = GLINTPTR(pScrn);
CARD32 LocalMemCaps;
TRACE_ENTER("Permedia3PreInit");
if (IS_J2000) {
unsigned char m,n,p;
if (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_GAMMA)
GLINT_SLOW_WRITE_REG(GCSRSecondaryGLINTMapEn, GCSRAperture);
/* Memory timings for the Appian J2000 board.
* This is needed for the second head which is left un-initialized
* by the bios, thus freezing the machine. */
GLINT_SLOW_WRITE_REG(0x02e311B8, PM3LocalMemCaps);
GLINT_SLOW_WRITE_REG(0x07424905, PM3LocalMemTimings);
GLINT_SLOW_WRITE_REG(0x0c000003, PM3LocalMemControl);
GLINT_SLOW_WRITE_REG(0x00000061, PM3LocalMemRefresh);
GLINT_SLOW_WRITE_REG(0x00000000, PM3LocalMemPowerDown);
/* Let's program the K, M and S Clocks to the same values as the bios
* does for first head :
* - KClk and MClk are 105Mhz.
* - S Clock is set to PClk.
* Note 1 : pGlint->RefClock is not set yet, so use 14318 instead.
* Note 2 : KClk gets internally halved, so we need to double it.
*/
(void) PM3DAC_CalculateClock(2*105000, 14318, &m,&n,&p);
Permedia2vOutIndReg(pScrn, PM3RD_KClkPreScale, 0x00, m);
Permedia2vOutIndReg(pScrn, PM3RD_KClkFeedbackScale, 0x00, n);
Permedia2vOutIndReg(pScrn, PM3RD_KClkPostScale, 0x00, p);
Permedia2vOutIndReg(pScrn, PM3RD_KClkControl, 0x00,
PM3RD_KClkControl_STATE_RUN |
PM3RD_KClkControl_SOURCE_PLL |
PM3RD_KClkControl_ENABLE);
Permedia2vOutIndReg(pScrn, PM3RD_MClkControl, 0x00,
PM3RD_MClkControl_STATE_RUN |
PM3RD_MClkControl_SOURCE_KCLK |
PM3RD_MClkControl_ENABLE);
Permedia2vOutIndReg(pScrn, PM3RD_SClkControl, 0x00,
PM3RD_SClkControl_STATE_RUN |
PM3RD_SClkControl_SOURCE_PCLK |
PM3RD_SClkControl_ENABLE);
}
#if defined(__alpha__)
/*
* On Alpha, we have to "int10" secondary VX1 cards early;
* otherwise, some information taken from registers, like
* memory size, is incorrect.
*/
if (!xf86IsPrimaryPci(pGlint->PciInfo)) {
if ( IS_QVX1 ) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"VX1 secondary enabling VGA before int10\n");
/* Enable VGA on the current card. */
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xf8);
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xf4);
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xfc);
/* The card we are on should be VGA-enabled now, so run int10. */
if (xf86LoadSubModule(pScrn, "int10")) {
xf86Int10InfoPtr pInt;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Initializing int10\n");
pInt = xf86InitInt10(pGlint->pEnt->index);
xf86FreeInt10(pInt);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"VX1 secondary disabling VGA after int10\n");
/* Finally, disable VGA on the current card. */
PCI_WRITE_BYTE(pGlint->PciInfo, 0x70, 0xf8);
PCI_WRITE_BYTE(pGlint->PciInfo, 0x01, 0xf4);
PCI_WRITE_BYTE(pGlint->PciInfo, 0x00, 0xfc);
}
}
#endif /* __alpha__ */
/* If we have SDRAM instead of SGRAM, we have to do some things
differently in the FillRectSolid code. */
LocalMemCaps = GLINT_READ_REG(PM3LocalMemCaps);
pGlint->PM3_UsingSGRAM = !(LocalMemCaps & PM3LocalMemCaps_NoWriteMask);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using %s memory\n",
pGlint->PM3_UsingSGRAM ? "SGRAM" : "SDRAM");
TRACE_EXIT("Permedia3PreInit");
}