void Prs_ManWriteVerilogArray( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd )
{
int i, Sig;
assert( Vec_IntSize(vSigs) > 0 );
Vec_IntForEachEntryStartStop( vSigs, Sig, i, Start, Stop )
{
if ( fOdd && !(i & 1) )
continue;
Prs_ManWriteVerilogSignal( pFile, p, Sig );
fprintf( pFile, "%s", i == Stop - 1 ? "" : ", " );
}
}
void Prs_ManWriteVerilogArray2( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t * vSigs )
{
int i, FormId, ActSig;
assert( Vec_IntSize(vSigs) % 2 == 0 );
Vec_IntForEachEntryDouble( vSigs, FormId, ActSig, i )
{
fprintf( pFile, "." );
fprintf( pFile, "%s", Prs_NtkStr(p, FormId) );
fprintf( pFile, "(" );
Prs_ManWriteVerilogSignal( pFile, p, ActSig );
fprintf( pFile, ")%s", (i == Vec_IntSize(vSigs) - 2) ? "" : ", " );
}
void Prs_ManWriteVerilogArray( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t * vSigs, int fOdd )
{
int i, Sig, fFirst = 1;
assert( Vec_IntSize(vSigs) > 0 );
Vec_IntForEachEntry( vSigs, Sig, i )
{
if ( fOdd && !(i & 1) )
continue;
fprintf( pFile, "%s", fFirst ? "" : ", " );
Prs_ManWriteVerilogSignal( pFile, p, Sig );
fFirst = 0;
}
}
