void Prs_ManWriteVerilogSignal( FILE * pFile, Prs_Ntk_t * p, int Sig )
{
int Value = Abc_Lit2Var2( Sig );
Prs_ManType_t Type = Abc_Lit2Att2( Sig );
if ( Type == CBA_PRS_NAME || Type == CBA_PRS_CONST )
fprintf( pFile, "%s", Prs_NtkStr(p, Value) );
else if ( Type == CBA_PRS_SLICE )
fprintf( pFile, "%s%s", Prs_NtkStr(p, Prs_SliceName(p, Value)), Prs_NtkStr(p, Prs_SliceRange(p, Value)) );
else if ( Type == CBA_PRS_CONCAT )
Prs_ManWriteVerilogConcat( pFile, p, Value );
else assert( 0 );
}
char * Prs_ObjGetName( Prs_Ntk_t * p, int NameId )
{
char * pName = Prs_NtkStr(p, NameId);
if ( pName == NULL )
return pName;
if ( Prs_NameIsLegalInVerilog(pName, NameId) )
return pName;
return Vec_StrPrintF( Abc_NamBuffer(p->pStrs), "\\%s ", pName );
}
void Prs_ManWriteVerilogArray2( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t * vSigs )
{
int i, FormId, ActSig;
assert( Vec_IntSize(vSigs) % 2 == 0 );
Vec_IntForEachEntryDouble( vSigs, FormId, ActSig, i )
{
fprintf( pFile, "." );
fprintf( pFile, "%s", Prs_NtkStr(p, FormId) );
fprintf( pFile, "(" );
Prs_ManWriteVerilogSignal( pFile, p, ActSig );
fprintf( pFile, ")%s", (i == Vec_IntSize(vSigs) - 2) ? "" : ", " );
}
